Rajsaktish Sankaranarayanan

According to our database, Rajsaktish Sankaranarayanan authored at least 3 papers between 2012 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Chip Package Co-design and Physical Verification for Heterogeneous Integration.

Rajsaktish Sankaranarayanan, Archanna Srinivasan, Arch Zaliznyak, Sreelekha Mittai

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2017

Energy Savings and Performance Improvement in Subthreshold Using Adaptive Body Bias.

Rajsaktish Sankaranarayanan, Matthew R. Guthaus

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2012

A single-VDD ultra-low energy sub-threshold FPGA.

Rajsaktish Sankaranarayanan, Matthew R. Guthaus

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012