Rakesh H. Patel

According to our database1, Rakesh H. Patel authored at least 11 papers between 2002 and 2009.

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Bibliography

2009
Nonlinear behavior study in digital bang-bang PLL.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Session 21 - Leveraging the third Dimension.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations.
Proceedings of the 43rd Design Automation Conference, 2006

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Design considerations for 2nd-order and 3rd-order bang-bang CDR loops.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Multi-protocol embedded PCS IP in a FPGA-SOC.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A signal integrity-based link performance simulation platform.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Nanometer design intricacies.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Power estimation and thermal budgeting methodology for FPGAs.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2002
Interconnect enhancements for a high-speed PLD architecture.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002


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