Aria Eshraghi

According to our database1, Aria Eshraghi authored at least 11 papers between 1994 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A 192-Virtual-Receiver 77/79GHz GMSK Code-Domain MIMO Radar System-on-Chip.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2004
A comparative analysis of parallel delta-sigma ADC architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

2003
A time-interleaved parallel /ΔΣ A/D converter.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

2002
A CMOS transconductor with 80-dB SFDR up to 10 MHz.
IEEE J. Solid State Circuits, 2002

2001
A 3.3 V transconductor in 0.35 μm CMOS with 80 dB SFDR up to 10 MHz.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
A 14-bit current-mode ΣΔ DAC based upon rotated data weighted averaging.
IEEE J. Solid State Circuits, 2000

1999
A spurious-free delta-sigma DAC using rotated data weighted averaging.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998
A Nyquist-rate delta-sigma A/D converter.
IEEE J. Solid State Circuits, 1998

1994
Design of a new squaring function for the Viterbi algorithm.
IEEE J. Solid State Circuits, September, 1994

Asynchronus Implementation for the Add Compare Select Processor for Communication Systems.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Compact and Accurate MOST Model for Analog Circuit Hand Calculations.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994


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