Terri S. Fiez

According to our database1, Terri S. Fiez authored at least 88 papers between 1993 and 2020.

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Awards

IEEE Fellow

IEEE Fellow 2005, "For contributions to analog and mixed-signal integrated circuits.".

Timeline

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Bibliography

2020
A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique.
IEEE J. Solid State Circuits, 2020

2019
A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4<sup>th</sup> order CT-ΔΣ modulator with 2<sup>nd</sup> order noise-shaping and pipelined SAR-VCO based quantizer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
2017 IEEE Education Society Awards, 2017 Frontiers in Education Conference Awards, and Selected IEEE Awards.
IEEE Trans. Educ., 2018

A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation.
IEEE J. Solid State Circuits, 2018

A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Fast start-up analysis of resonator based oscillators using a power generation method.
IET Circuits Devices Syst., 2016

JetNet: A proposed protocol for reliable packet delivery in low-power IoT applications.
Proceedings of the 3rd IEEE World Forum on Internet of Things, 2016

2015
350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS.
IEEE J. Solid State Circuits, 2015

A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator.
IEEE J. Solid State Circuits, 2015

2014
Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with -76dBm sensitivity for high data rate wireless sensor networks.
Proceedings of the Symposium on VLSI Circuits, 2014

12.9 A 1.55×0.85mm<sup>2</sup> 3ppm 1.0μA 32.768kHz MEMS-based oscillator.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW.
IEEE J. Solid State Circuits, 2013

A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks.
IEEE J. Solid State Circuits, 2013

2012
Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques.
Proceedings of the 25th International Conference on VLSI Design, 2012

A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
A Multiple-Input Boost Converter for Low-Power Energy Harvesting.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 250 mV, 352 μ W GPS Receiver RF Front-End in 130 nm CMOS.
IEEE J. Solid State Circuits, 2011

A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency.
IEEE J. Solid State Circuits, 2011

A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
An Ultralow-Power Receiver for Wireless Sensor Networks.
IEEE J. Solid State Circuits, 2010

A new zero-optimization scheme for noise-coupled ΔΣ ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 475 mV, 4.9 GHz enhanced swing differential Colpitts VCO in 130 nm CMOS with an FoM of 196.2 dBc/Hz.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Frequency-Dependent Sampling Linearity.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A Novel Low Power Hybrid Loop Filter for Continuous-time Sigma-delta Modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks.
IEEE J. Solid State Circuits, 2008

A 900-MHz low-power transmitter with fast frequency calibration for wireless sensor networks.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A 0.4 nJ/b 900MHz CMOS BFSK super-regenerative receiver.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth.
IEEE J. Solid State Circuits, 2007

A Low Power BFSK Super-Regenerative Transceiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Finding a Way: What can Computer Science Education Do?
Proceedings of the 2007 International Conference on Frontiers in Education: Computer Science & Computer Engineering, 2007

Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Sizing Ground Taps to Minimize Substrate Noise Coupling in RF LNAs.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Efficient Far-Field Radio Frequency Power Conversion System for Passively Powered Sensor Networks.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Prediction and Characterization of Frequency Dependent MOS Switch Linearity and the Design Implications.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Accurate and efficient simulation of synchronous digital switching noise in systems on a chip.
IEEE Trans. Very Large Scale Integr. Syst., 2005

On the numerical stability of Green's function for substrate coupling in integrated circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A green function-based parasitic extraction method for inhomogeneous substrate layers.
Proceedings of the 42nd Design Automation Conference, 2005

2004
An efficient formulation for substrate parasitic extraction accounting for nonuniform current distribution.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Process-insensitive low-power design of switched-capacitor integrators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A comparative analysis of parallel delta-sigma ADC architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A noise-shaped switching power supply using a delta-sigma modulator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Silencer!: a tool for substrate noise coupling analysis.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

An improved Z-parameter macro model for substrate noise coupling.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A physical and analytical model for substrate noise coupling analysis.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A predictive methodology for accurate substrate parasitic extraction.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A variable gain high linearity low power baseband filter for WLAN.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An accurate and efficient estimation of switching noise in synchronous digital circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A 0.35µm current-mode T/H with -81dB THD.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Digital noise coupling mechanisms in a 2.4 GHz LNA for heavily and lightly doped CMOS substrates.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Using an integrated platform for learning™ to reinvent engineering education.
IEEE Trans. Educ., 2003

Enhancing the freshman and sophomore ECE student experience using a platform for learning™.
IEEE Trans. Educ., 2003

Coupled Simulation of Circuit and Piezoelectric Laminates.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002
An efficient modeling approach for substrate noise coupling analysis.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Dynamic element matching in low oversampling delta sigma ADCs.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

An efficient parallel delta-sigma ADC utilizing a shared multi-bit quantizer.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Analysis of jitter in ring oscillators due to deterministic noise.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

1999
Design-oriented substrate noise coupling macromodels for heavily doped CMOS processes.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Switched-capacitor integrator design optimizing for power and process variations.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A scalable substrate noise coupling model for mixed-signal ICs.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
CMOS analog circuit stack generation with matching constraints.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
A low voltage CMOS current source.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

1995
PWM and PCM Techniques for Control of Digitally Programmable Switching Power Supplies.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Improved Delta-Sigma DAC Linearity Using Data Weighted Averaging.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
A 12 Bit, 2V Current-Mode Pipelined A/D Converter Nonlinearity.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Asynchronus Implementation for the Add Compare Select Processor for Communication Systems.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Compact and Accurate MOST Model for Analog Circuit Hand Calculations.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Simulation of Switched-Current Systems.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Stability Analysis of High-order Modulators for Delta-Sigma ADCs.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


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