Arijit Dutta

According to our database, Arijit Dutta authored at least 11 papers between 2001 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A Hybrid Deep Learning Model-Based Intrusion Detection System for Emergency Planning Using IoT-Network.

Inam Ullah Khan, Muhammad Yaseen Ayub, Asrin Abdollahi, Arijit Dutta

Proceedings of the International Conference on Information and Communication Technologies for Disaster Management, 2023

2021

MProve+: Privacy Enhancing Proof of Reserves Protocol for Monero.

Arijit Dutta, Suyash Bagad, Saravanan Vijayakumaran

IEEE Trans. Inf. Forensics Secur., 2021

Assisting fog-cloud computing with an adaptive traffic awareness resource provisioning algorithm for health data.

Luina Pani, Arijit Dutta, Chinmaya Misra, Ruben Roy

Proceedings of the 19th OITS International Conference on Information Technology, 2021

Finite Buffer Queueing System Performance Study with Multi Heterogeneous Fog Architecture.

Arijit Dutta, Luina Pani, Chinmaya Misra, Ruben Roy

Proceedings of the 19th OITS International Conference on Information Technology, 2021

2019

Revelio: A MimbleWimble Proof of Reserves Protocol.

Arijit Dutta, Saravanan Vijayakumaran

IACR Cryptol. ePrint Arch., 2019

Nummatus: A Privacy Preserving Proof of Reserves Protocol for Quisquis.

Arijit Dutta, Arnab Jana, Saravanan Vijayakumaran

Proceedings of the Progress in Cryptology - INDOCRYPT 2019, 2019

MProve: A Proof of Reserves Protocol for Monero Exchanges.

Arijit Dutta, Saravanan Vijayakumaran

Proceedings of the 2019 IEEE European Symposium on Security and Privacy Workshops, 2019

2018

MProve: A Proof of Assets Protocol for Monero Exchanges.

Arijit Dutta, Saravanan Vijayakumaran

IACR Cryptol. ePrint Arch., 2018

2008

Penalty for power reduction -: performance or schedule or yield?

Bodhisatya Sarker, Jaswinder Ahuja, Arijit Dutta, Srinath D., Kaip Sridhar, Radhakrishnan Nair, Jayant Lahiri

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2001

Sub-100 nm CMOS circuit performance with high-K gate dielectrics.

Nihar R. Mohapatra, Arijit Dutta, G. Sridhar, Madhav P. Desai, V. Ramgopal Rao

Microelectron. Reliab., 2001

Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics.

Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai, V. Ramgopal Rao

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001