Nihar R. Mohapatra

According to our database, Nihar R. Mohapatra authored at least 25 papers between 2001 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

K-means Clustering with ANN based Classification to Predict Current-Voltage Characteristics of Advanced FETs.

Om Maheshwari, Dev Vyas, Nihar Ranjan Mohapatra

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

Process Voltage Temperature Variability Estimation of Tunneling Current for Band-to-Band-Tunneling based Neuron.

Shubham Patil, Anand Sharma, Gaurav R, Abhishek Kadam, Ajay Kumar Singh, Sandip Lashkare, Nihar Ranjan Mohapatra, Udayan Ganguly

CoRR, 2023

2022

Dispersion in Placement: Quantification and Insights.

Satyajit Mohapatra, Nihar Ranjan Mohapatra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

High Resolution Temperature Sensor Signal Processing ASIC for Cryo-Cooler Electronics.

Anuj Srivastava, Nishant Kumar, Nihar Ranjan Mohapatra, Hari Shankar Gupta

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2021

Behavior of LDMOS transistors at cryogenic temperature - An experiment based analysis.

Kaushal Kumari Neeraj, Nihar Ranjan Mohapatra

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

2020

Gradient Error Compensation in SC-MDACs.

Satyajit Mohapatra, Nihar Ranjan Mohapatra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

The Design of Ultra Low Power SAR ADC for Implantable Cardioverter Defibrillator (ICD).

Satyajit Mohapatra, Nihar Ranjan Mohapatra

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

2019

Band-to-Band Tunneling based Ultra-Energy Efficient Silicon Neuron.

Tanmay Chavan, Sangya Dutta, Nihar R. Mohapatra, Udayan Ganguly

CoRR, 2019

A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC.

Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra, Sanjeev Mehta, Arup Roy Chowdhury, Nisha Pandya

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Gate MOS Transistors.

Amratansh Gupta, Mohit Ganeriwala, Nihar Ranjan Mohapatra

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical Applications.

Yadukrishnan Mekkattillam, Satyajit Mohapatra, Nihar R. Mohapatra

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Capacitance and Surface Potential Model for III-V Double-Gate FET.

Sarath Chandran G. M, Mohit D. Ganeriwala, Nihar Ranjan Mohapatra

Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

2018

The HotSpot Compensation in High Speed Data Converters.

Satyajit Mohapatra, Nihar Ranjan Mohapatra

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Mismatch Resilient 3.5-Bit MDAC with MCS-CFCS.

Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

An Ultra Energy Efficient Neuron enabled by Tunneling in Sub-threshold Regime on a Highly Manufacturable 32 nm SOI CMOS Technology.

Tanmay Chavan, S. Dutta, Nihar R. Mohapatra, Udayan Ganguly

Proceedings of the 76th Device Research Conference, 2018

2017

A 64b/66b Line Encoding for High Speed Serializers.

Satyajit Mohapatra, Hari Shanker Gupta, Jatindeep Singh, Nihar Ranjan Mohapatra

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Low-Power Sequential Circuit Design Using Work-Function Engineered FinFETs.

Ashish Soni, Abhijit Umap, Nihar R. Mohapatra

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Performance Optimized 64b/66b Line Encoding Technique for High Speed SERDES Devices.

Jatindeep Singh, Satyajit Mohapatra, Nihar Ranjan Mohapatra

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Trap-assisted carrier transport through the multi-stack gate dielectrics of HKMG nMOS transistors: A compact model.

Apoorva Ojha, Nihar R. Mohapatra

Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016

Analysis and Modeling of Stress over Layer Induced Threshold Voltage Shift in HKMG nMOS Transistors.

Apoorva Ojha, Narendra Parihar, Nihar R. Mohapatra

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel array.

Hari Shanker Gupta, Satyajit Mohapatra, Nihar R. Mohapatra, Dinesh Kumar Sharma

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2003

Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics.

Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits.

D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2001

Sub-100 nm CMOS circuit performance with high-K gate dielectrics.

Nihar R. Mohapatra, Arijit Dutta, G. Sridhar, Madhav P. Desai, V. Ramgopal Rao

Microelectron. Reliab., 2001

Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics.

Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai, V. Ramgopal Rao

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001