Madhav P. Desai

According to our database, Madhav P. Desai authored at least 46 papers between 1993 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

An evaluation of a microprocessor with two independent hardware execution threads coupled through a shared cache.

Madhav P. Desai

CoRR, 2023

2022

Sitar: A Cycle-based Discrete-Event Simulation Framework for Architecture Exploration.

Neha V. Karanjkar, Madhav P. Desai

Proceedings of the 12th International Conference on Simulation and Modeling Methodologies, 2022

2021

An efficient reverse-lookup table based strategy for solving the synonym and cache coherence problem in virtually indexed, virtually tagged caches.

Madhav P. Desai, Aniket Anand Deshmukh

CoRR, 2021

2018

Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology.

Nanditha P. Rao, Madhav P. Desai

Microelectron. J., 2018

2017

Neutron-induced strike: Study of multiple node charge collection in 14nm FinFETs.

Nanditha P. Rao, Madhav P. Desai

CoRR, 2017

2016

Higher likelihood of multiple bit-flips due to neutron-induced strikes on logic gates.

Nanditha P. Rao, Madhav P. Desai

CoRR, 2016

On Continuous-space Embedding of Discrete-parameter Queuing Systems.

Neha V. Karanjkar, Madhav P. Desai

CoRR, 2016

Projective cofactor decompositions of Boolean functions and the satisfiability problem.

Madhav P. Desai, Virendra Sule

CoRR, 2016

Low-Power, Low-Latency Hermite Polynomial Characterization of Heartbeats Using a Field-Programmable Gate Array.

Kartik Lakhotia, Gabriel Caffarena, Alberto Gil, David G. Márquez, Abraham Otero, Madhav P. Desai

Proceedings of the Bioinformatics and Biomedical Engineering, 2016

2015

An Approach to Discrete Parameter Design Space Exploration of Multi-core Systems Using a Novel Simulation Based Interpolation Technique.

Neha V. Karanjkar, Madhav P. Desai

Proceedings of the 23rd IEEE International Symposium on Modeling, 2015

A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients.

Nanditha P. Rao, Madhav P. Desai

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014

On the likelihood of multiple bit upsets in logic circuits.

Nanditha P. Rao, Shahbaz Sarik, Madhav P. Desai

CoRR, 2014

Optimization of Discrete-parameter Multiprocessor Systems using a Novel Ergodic Interpolation Technique.

Neha V. Karanjkar, Madhav P. Desai

CoRR, 2014

Generalized cofactors and decomposition of Boolean satisfiability problems.

Madhav P. Desai, Virendra Sule

CoRR, 2014

Inner Loop Optimizations in Mapping Single Threaded Programs to Hardware.

Madhav P. Desai

CoRR, 2014

2012

The Click2NetFPGA Toolchain.

Teemu Rinta-aho, Mika Karlstedt, Madhav P. Desai

Proceedings of the 2012 USENIX Annual Technical Conference, 2012

2010

On Cycles in Random Graphs

Madhav P. Desai

CoRR, 2010

Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems.

Gautam Hazari, Madhav P. Desai, G. Srinivas

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems.

Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Kunal P. Ghosh, Kavi Arya, Madhav P. Desai

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Learning based address mapping for improving the performance of memory subsystems.

Pratyush Kumar, Madhav P. Desai

Proceedings of the 17th Annual Meeting of the IEEE/ACM International Symposium on Modelling, 2009

2007

Parallelization of DC Analysis through Multiport Decomposition.

Gaurav Trivedi, Madhav P. Desai, H. Narayanan

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs.

Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Madhav P. Desai

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

On the Impact of Address Space Assignment on Performance in Systems-on-Chip.

Gautam Hazari, Madhav P. Desai, H. Kasture

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

Fast DC Analysis and Its Application to Combinatorial Optimization Problems.

Gaurav Trivedi, Madhav P. Desai, H. Narayanan

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005

On Range Matrices and Wireless Networks in d Dimensions.

Madhav P. Desai, D. Manjunath

Proceedings of the 3rd International Symposium on Modeling and Optimization in Mobile, 2005

Variance Reduction in Monte Carlo Capacitance Extraction.

Shabbir H. Batterywala, Madhav P. Desai

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2004

On Buffering Schemes for Long Multi-Layer Nets.

Vani Prasad, Madhav P. Desai

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Distributed and Pipelined Controller for a Modular and Scalable Hardware Emulator.

Aditya Mittal, Madhav P. Desai

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Novel Technique Towards Eliminating the Global Clock in VLSI Circuits.

Gautam Hazari, Madhav P. Desai, Apoorv Gupta, Supratik Chakraborty

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003

Reconfigurable finite-state machine based IP lookup engine for high-speed router.

Madhav P. Desai, Ritu Gupta, Abhay Karandikar, Kshitiz Saxena, Vinayak Samant

IEEE J. Sel. Areas Commun., 2003

The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function.

Madhav P. Desai, H. Narayanan, Sachin B. Patkar

Discret. Appl. Math., 2003

Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy.

Vani Prasad, Madhav P. Desai

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics.

Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2002

On the connectivity in finite ad hoc networks.

Madhav P. Desai, D. Manjunath

IEEE Commun. Lett., 2002

Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches.

Maryam Shojaei Baghini, Madhav P. Desai

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2001

Sub-100 nm CMOS circuit performance with high-K gate dielectrics.

Nihar R. Mohapatra, Arijit Dutta, G. Sridhar, Madhav P. Desai, V. Ramgopal Rao

Microelectron. Reliab., 2001

An On-Chip Coupling Capacitance Measurement Technique.

Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics.

Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai, V. Ramgopal Rao

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000

Inductance Characterization of Small Interconnects Using Test-Signal Method.

Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999

A State Assignment Scheme Targeting Performance and Area.

B. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Decomposition of Finite State Machines for Area, Delay Minimization.

Rupesh S. Shelar, Madhav P. Desai, H. Narayanan

Proceedings of the IEEE International Conference On Computer Design, 1999

1998

Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor.

Nevine Nassif, Madhav P. Desai, Dale H. Hall

Proceedings of the 35th Conference on Design Automation, 1998

1996

A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation.

Madhav P. Desai, Yao-Tsung Yen

Proceedings of the 33st Conference on Design Automation, 1996

Sizing of Clock Distribution Networks for High Performance CPU Chips.

Madhav P. Desai, Radenko Cvijetic, James Jensen

Proceedings of the 33st Conference on Design Automation, 1996

1994

A characterization of the smallest eigenvalue of a graph.

Madhav P. Desai, Vasant B. Rao

J. Graph Theory, 1994

1993

On the Convergence of Reversible Markov Chains.

Madhav P. Desai, Vasant B. Rao

SIAM J. Matrix Anal. Appl., October, 1993