Uddalak Bhattacharya

According to our database, Uddalak Bhattacharya authored at least 27 papers between 1994 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology.

Stafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, Jaydeep P. Kulkarni

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2020

Compiler compatible 5.66 Mb/mm² 8T 1R1W register file in 14 nm FinFET technology.

Arindrajit Ghosh, Uddalak Bhattacharya, Manish Kumar, Swapna Banerjee

Integr., 2020

2018

Contention free delayed keeper for high density large signal sensing memory compiler.

Arindrajit Ghosh, Uddalak Bhattacharya, Swapna Banerjee

Integr., 2018

2017

A 0.9-μm² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming.

Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Salil Manohar Rajarshi, Lei Jiang, Uddalak Bhattacharya

IEEE J. Solid State Circuits, 2017

2016

A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS.

Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang

IEEE J. Solid State Circuits, 2016

A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry.

Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Xiaofei Wang, Uddalak Bhattacharya, Kevin Zhang

IEEE J. Solid State Circuits, 2016

A 0.9um² 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating.

Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya, Kevin Zhang

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015

Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process.

Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang

Proceedings of the Symposium on VLSI Circuits, 2015

A 0.094um² high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist.

Kyung-Hoae Koo, Liqiong Wei, John Keane, Uddalak Bhattacharya, Eric A. Karl, Kevin Zhang

Proceedings of the Symposium on VLSI Circuits, 2015

17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology.

Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Uddalak Bhattacharya, Kevin Zhang

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013

A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry.

Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Mesut Meterelliyoz, John Keane, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr

IEEE J. Solid State Circuits, 2013

2012

A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry.

Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation.

Pramod Kolar, Eric Karl, Uddalak Bhattacharya, Fatih Hamzaoglu, Henry Nho, Yong-Gee Ng, Yih Wang, Kevin Zhang

IEEE J. Solid State Circuits, 2011

Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design.

Fatih Hamzaoglu, Yih Wang, Pramod Kolar, Liqiong Wei, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang

IEEE Des. Test Comput., 2011

2010

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management.

Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr

IEEE J. Solid State Circuits, 2010

A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation.

Hyunwoo Nho, Pramod Kolar, Fatih Hamzaoglu, Yih Wang, Eric Karl, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology.

Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr

IEEE J. Solid State Circuits, 2009

A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management.

Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.

Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr

IEEE J. Solid State Circuits, 2008

A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology.

Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications.

Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Yih Zhang, Kevin Zhang, Mark Bohr

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply.

Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr

IEEE J. Solid State Circuits, 2006

2005

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction.

Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr

IEEE J. Solid State Circuits, 2005

1999

An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin.

Cangsang Zhao, Uddalak Bhattacharya, Martin Denham, Jim Kolousek, Yi Lu, Yong-Gee Ng, Novat Nintunze, Kamal Sarkez, Hemmige D. Varadarajan

IEEE J. Solid State Circuits, 1999

1996

Multiplexer/demultiplexer IC technology for 100 Gb/s fiber-optic transmission.

Rajasekhar Pullela, Uddalak Bhattacharya, Scott T. Allen, Mark J. W. Rodwell

IEEE J. Solid State Circuits, 1996

1995

Design and performance of multistage GaAs dynamic logic.

Fleming Hoeg, Stephen I. Long, Uddalak Bhattacharya

IEEE J. Solid State Circuits, May, 1995

1994

Active and nonlinear wave propagation devices in ultrafast electronics and optoelectronics.

Mark J. W. Rodwell, Scott T. Allen, Ruai Y. Yu, Michael G. Case, Uddalak Bhattacharya, Madhukar Reddy, Eric Carman, Masayuki Kamegawa, Yoshiyuki Konishi, Joe Pusl, Rajasekhar Pullela

Proc. IEEE, 1994