Aritra Dasgupta

Orcid: 0000-0002-0786-9185

Affiliations:
  • University of Florida, Gainesville, FL, USA


According to our database1, Aritra Dasgupta authored at least 19 papers between 2022 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
LASA: Enhancing SoC Security Verification with LLM-Aided Property Generation.
CoRR, June, 2025

Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation.
CoRR, May, 2025

SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs.
CoRR, April, 2025

Library-Attack: Reverse Engineering Approach for Evaluating Hardware IP Protection.
CoRR, January, 2025

HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025

Towards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon Stages.
Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking.
Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

2024
SPELL: An End-to-End Tool Flow for LLM-Guided Secure SoC Design for Embedded Systems.
IEEE Embed. Syst. Lett., December, 2024

FDPUF: Frequency-Domain PUF for Robust Authentication of Edge Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024

Pasteables: A Flexible, Stick-and-Peel Smart Sensing Platform for Edge Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Splitting the Secrets: A Cooperative Trust Model for System-on-Chip Designs with Untrusted IPs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

IP Security in Structured ASIC: Challenges and Prospects.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

Navigating SoC Security Landscape on LLM-Guided Paths.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

LISA: A Multi-Layered Iterative Framework for Hardening Obfuscation with Modular Unit Transformations.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection.
Proceedings of the 33rd IEEE Asian Test Symposium, 2024

2023
DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protection.
CoRR, 2023

An Exploration of ATPG Methods for Redacted IP and Reconfigurable Hardware.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

2022
SEVA: Structural Analysis based Security Evaluation of Sequential Locking.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022


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