Aritra Dasgupta

CoRR, April, 2026

CRISP: Platform-Agnostic Unified Reconfigurable Hardware Security Primitive.

[BibT_eX]

[DOI]

Proceedings of the 27th International Symposium on Quality Electronic Design, 2026

PROM: Protection against Reverse Engineering Attacks through Programmable Logic Macros.

[BibT_eX]

[DOI]

Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2026

2025

LATTE: Library Attack for Evaluating Hardware IP Protections Against Reverse Engineering.

[BibT_eX]

[DOI]

IEEE Des. Test, December, 2025

Intelligent Graybox Fuzzing via ATPG-Guided Seed Generation and Submodule Analysis.

[BibT_eX]

[DOI]

CoRR, September, 2025

LASA: Enhancing SoC Security Verification with LLM-Aided Property Generation.

[BibT_eX]

[DOI]

CoRR, June, 2025

Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation.

[BibT_eX]

[DOI]

CoRR, May, 2025

SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs.

[BibT_eX]

[DOI]

CoRR, April, 2025

Library-Attack: Reverse Engineering Approach for Evaluating Hardware IP Protection.

[BibT_eX]

[DOI]

CoRR, January, 2025

HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2025

Towards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon Stages.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

LASSO: LLM-Aided Security Property Generation for Assertion-based SoC Verification.

[BibT_eX]

[DOI]

Proceedings of the 7th ACM/IEEE Symposium on Machine Learning for CAD, 2025

LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2025

FV-PAL: Scalable Formal Verification through Partitioning and LLM-Guided Property Generation.

[BibT_eX]

[DOI]

Prabuddha Chakraborty

Proceedings of the 43rd IEEE International Conference on Computer Design, 2025

PROFUZZ: Directed Graybox Fuzzing via Module Selection and ATPG-Guided Seed Generation.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

2024

SPELL: An End-to-End Tool Flow for LLM-Guided Secure SoC Design for Embedded Systems.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., December, 2024

FDPUF: Frequency-Domain PUF for Robust Authentication of Edge Devices.

[BibT_eX]

[DOI]

Shubhra Deb Paul

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024

Pasteables: A Flexible, Stick-and-Peel Smart Sensing Platform for Edge Applications.

[BibT_eX]

[DOI]

Reiner N. Dizon-Paradis

Rohan Reddy Kalavakonda

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Splitting the Secrets: A Cooperative Trust Model for System-on-Chip Designs with Untrusted IPs.

[BibT_eX]

[DOI]

Prabuddha Chakraborty

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

IP Security in Structured ASIC: Challenges and Prospects.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

Navigating SoC Security Landscape on LLM-Guided Paths.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

LISA: A Multi-Layered Iterative Framework for Hardening Obfuscation with Modular Unit Transformations.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE Asian Test Symposium, 2024

2023

DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protection.

[BibT_eX]

[DOI]