Swarup Bhunia

According to our database1, Swarup Bhunia authored at least 274 papers between 1999 and 2021.

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Bibliography

2021
On Database-Free Authentication of Microelectronic Components.
IEEE Trans. Very Large Scale Integr. Syst., 2021

FaultDroid: An Algorithmic Approach for Fault-Induced Information Leakage Analysis.
ACM Trans. Design Autom. Electr. Syst., 2021

Neural Storage: A New Paradigm of Elastic Memory.
CoRR, 2021

A Smart Mask for Active Defense Against Coronaviruses and Other Airborne Pathogens.
IEEE Consumer Electron. Mag., 2021

2020
Low Power Unsupervised Anomaly Detection by Nonparametric Modeling of Sensor Statistics.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Hidden in Plaintext: An Obfuscation-based Countermeasure against FPGA Bitstream Tampering Attacks.
ACM Trans. Design Autom. Electr. Syst., 2020

Resilient System-on-Chip Designs With NoC Fabrics.
IEEE Trans. Inf. Forensics Secur., 2020

FEDS: Comprehensive Fault Attack Exploitability Detection for Software Implementations of Block Ciphers.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

SAFARI: Automatic Synthesis of Fault-Attack Resistant Block Cipher Implementations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Guest Editorial: ACM JETC Special Issue on New Trends in Nanolectronic Device, Circuit, and Architecture Design: Part 2.
ACM J. Emerg. Technol. Comput. Syst., 2020

Introduction to the Special Issue on New Trends in Nanoelectronic Device, Circuit, and Architecture Design, Part 1.
ACM J. Emerg. Technol. Comput. Syst., 2020

Hardware Obfuscation and Logic Locking: A Tutorial Introduction.
IEEE Des. Test, 2020

MeLPUF: Memory in Logic PUF.
CoRR, 2020

Scalable Attack-Resistant Obfuscation of Logic Circuits.
CoRR, 2020

SIGNED: A Challenge-Response Based Interrogation Scheme for Simultaneous Watermarking and Trojan Detection.
CoRR, 2020

Leveraging Domain Knowledge using Machine Learning for Image Compression in Internet-of-Things.
CoRR, 2020

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.
CoRR, 2020

An Automated Framework for Board-level Trojan Benchmarking.
CoRR, 2020

Low Power Unsupervised Anomaly Detection by Non-Parametric Modeling of Sensor Statistics.
CoRR, 2020

Trust Issues in Microelectronics: The Concerns and the Countermeasures.
IEEE Consumer Electron. Mag., 2020

P2C2: Peer-to-Peer Car Charging.
Proceedings of the 91st IEEE Vehicular Technology Conference, 2020

Fault Attack Detection in AES by Monitoring Power Side-Channel Statistics.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Trust Issues in COTS: The Challenges and Emerging Solution.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

SOLOMON: An Automated Framework for Detecting Fault Attack Vulnerabilities in Hardware.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
An Intrinsic and Database-Free Authentication by Exploiting Process Variation in Back-End Capacitors.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Guest Editorial: Special Section on Autonomous Intelligence for Security and Privacy Analytics.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Early Detection of Cardiovascular Diseases Using Wearable Ultrasound Device.
IEEE Consumer Electron. Mag., 2019

Eat, but Verify: Low-Cost Portable Devices for Food Safety Analysis.
IEEE Consumer Electron. Mag., 2019

Robust Authentication of Consumables With Extrinsic Tags and Chemical Fingerprinting.
IEEE Access, 2019

Special Session: Countering IP Security threats in Supply chain.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Quality Obfuscation for Error-Tolerant and Adaptive Hardware IP Protection.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future.
Proceedings of the IEEE International Test Conference, 2019

Runtime Integrity Verification in Cyber-physical Systems using Side-Channel Fingerprint.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

SCR-QRNG: Side-Channel Resistant Design using Quantum Random Number Generator.
Proceedings of the International Conference on Computer-Aided Design, 2019

SURF: Joint Structural Functional Attack on Logic Locking.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

Innovations in IoT for a Safe, Secure, and Sustainable Future.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

The Metric Matters: The Art of Measuring Trust in Electronics.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

New Frontiers in Hardware Security in the IoT Regime.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

Sweep to the Secret: A Constant Propagation Attack on Logic Locking.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

An Adaptable System-on-Chip Security Architecture for Internet of Things Applications.
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019

2018
Hardware-Enabled Pharmaceutical Supply Chain Security.
ACM Trans. Design Autom. Electr. Syst., 2018

Scalable Test Generation for Trojan Detection Using Side Channel Analysis.
IEEE Trans. Inf. Forensics Secur., 2018

System-on-Chip Platform Security Assurance: Architecture and Validation.
Proc. IEEE, 2018

Development and Evaluation of Hardware Obfuscation Benchmarks.
J. Hardw. Syst. Secur., 2018

Hardware Trojan attacks in embedded memory.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

An Open-Source Test-Bench for Autonomous Ultrasound Imaging.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify.
Proceedings of the IEEE International Test Conference, 2018

Robust Timing Attack Countermeasure on Virtual Hardware.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

ArtiFact: Architecture and CAD Flow for Efficient Formal Verification of SoC Security Policies.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Intrinsic and Database-free Watermarking in ICs by Exploiting Process and Design Dependent Variability in Metal-Oxide-Metal Capacitances.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Keynotes.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Internet of Things security: Are we paranoid enough?
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Hardware virtualization for protection against power analysis attack.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Securing the Systems of the Future - Techniques for a Shifting Attack Space.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

An automated configurable Trojan insertion framework for dynamic trust benchmarks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

SAIL: Machine Learning Guided Structural Analysis Attack on Hardware Obfuscation.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017
ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Security Assurance for System-on-Chip Designs With Untrusted IPs.
IEEE Trans. Inf. Forensics Secur., 2017

Guest Editors Introduction: Security of Beyond CMOS Devices: Issues and Opportunities.
IEEE Trans. Emerg. Top. Comput., 2017

SMA: A System-Level Mutual Authentication for Protecting Electronic Hardware and Firmware.
IEEE Trans. Dependable Secur. Comput., 2017

Energy-Efficient Adaptive Computing With Multifunctional Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Tunable and Lightweight On-Chip Event Detection for Implantable Bladder Pressure Monitoring Devices.
IEEE Trans. Biomed. Circuits Syst., 2017

Energy-Efficient Reconfigurable Hardware Accelerators for Data-Intensive Applications.
J. Low Power Electron., 2017

Benchmarking of Hardware Trojans and Maliciously Affected Circuits.
J. Hardw. Syst. Secur., 2017

A Security Perspective on Battery Systems of the Internet of Things.
J. Hardw. Syst. Secur., 2017

Editorial for the Introductory Issue of the <i>Journal of Hardware and Systems Security</i> (HaSS).
J. Hardw. Syst. Secur., 2017

Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications.
ACM J. Emerg. Technol. Comput. Syst., 2017

Golden-Free Hardware Trojan Detection with High Sensitivity Under Process Noise.
J. Electron. Test., 2017

A Uniquified Virtualization Approach to Hardware Security.
IEEE Embed. Syst. Lett., 2017

Adaptive ECC for Tailored Protection of Nanoscale Memory.
IEEE Des. Test, 2017

Interleaved logic-in-memory architecture for energy-efficient fine-grained data processing.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

ATAVE: A framework for automatic timing attack vulnerability evaluation.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A solitary protection measure against scan chain, fault injection, and power analysis attacks on AES.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Comparative Analysis of Hardware Obfuscation for IP Protection.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Authentication and traceability of food products through the supply chain using NQR spectroscopy.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

MUTARCH: Architectural diversity for FPGA device and IP security.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Security vulnerability analysis of design-for-test exploits for asset protection in SoCs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Mixed-granular architectural diversity for device security in the Internet of Things.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
DScanPUF: A Delay-Based Physical Unclonable Function Built Into Scan Chain.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Energy-Efficient Adaptive Hardware Accelerator for Text Mining Application Kernels.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Hardware Trojans: Lessons Learned after One Decade of Research.
ACM Trans. Design Autom. Electr. Syst., 2016

Wearables, Implants, and Internet of Things: The Technology Needs in the Evolving Landscape.
IEEE Trans. Multi Scale Comput. Syst., 2016

Design and Validation for FPGA Trust under Hardware Trojan Attacks.
IEEE Trans. Multi Scale Comput. Syst., 2016

Authentication of Medicines Using Nuclear Quadrupole Resonance Spectroscopy.
IEEE ACM Trans. Comput. Biol. Bioinform., 2016

SeMIA: Self-Similarity-Based IC Integrity Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

P-Val: Antifuse-Based Package-Level Defense Against Counterfeit ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

An Embedded Memory-Centric Reconfigurable Hardware Accelerator for Security Applications.
IEEE Trans. Computers, 2016

Real-Time Classification of Bladder Events for Effective Diagnosis and Treatment of Urinary Incontinence.
IEEE Trans. Biomed. Eng., 2016

Foundations of Secure Scaling (Dagstuhl Seminar 16342).
Dagstuhl Reports, 2016

Supply-Chain Security for Cyberinfrastructure [Guest editors' introduction].
Computer, 2016

Security validation in IoT space.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Robust bitstream protection in FPGA-based systems through low-overhead obfuscation.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Technical demonstration session: Software toolflow for FPGA bitstream obfuscation.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Active protection against PCB physical tampering.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

The power play: Security-energy trade-offs in the IoT regime.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

On detecting delay anomalies introduced by hardware trojans.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric (Abstact Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Real-time, autonomous bladder event classification and closed-loop control from single-channel pressure data.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

Current based PUF exploiting random variations in SRAM cells.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Exploiting design-for-debug for flexible SoC security architecture.
Proceedings of the 53rd Annual Design Automation Conference, 2016

MERS: Statistical Test Generation for Side-Channel Analysis based Trojan Detection.
Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, 2016

Ultralow-power data compression for implantable bladder pressure monitor: Algorithm and hardware implementation.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

JTAG-based robust PCB authentication for protection against counterfeiting attacks.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
SACCI: Scan-Based Characterization Through Clock Phase Sweep for Counterfeit Chip Detection.
IEEE Trans. Very Large Scale Integr. Syst., 2015

MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Guest Editors' Introduction: Wearables, Implants, and Internet of Things.
IEEE Trans. Multi Scale Comput. Syst., 2015

A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Guest Editorial Special Section on Hardware Security and Trust.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

IIPS: Infrastructure IP for Secure SoC Design.
IEEE Trans. Computers, 2015

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories.
Proc. IEEE, 2015

Exploring Spin Transfer Torque Devices for Unconventional Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Guest Editorial Computing in Emerging Technologies (Second Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

How Secure Are Printed Circuit Boards Against Trojan Attacks?
IEEE Des. Test, 2015

Robust counterfeit PCB detection exploiting intrinsic trace impedance variations.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems.
Proceedings of the 28th International Conference on VLSI Design, 2015

Energy-efficient reconfigurable computing using Spintronic memory.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

PiRA: IC authentication utilizing intrinsic variations in pin resistance.
Proceedings of the 2015 IEEE International Test Conference, 2015

A Flexible Architecture for Systematic Implementation of SoC Security Policies.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Correctness and security at odds: post-silicon validation of modern SoC designs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Self-correcting STTRAM under magnetic field attacks.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
A Variation-Aware Preferential Design Approach for Memory-Based Reconfigurable Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks.
IEEE Trans. Very Large Scale Integr. Syst., 2014

VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Implantable Ultrasonic Imaging Assembly for Automated Monitoring of Internal Organs.
IEEE Trans. Biomed. Circuits Syst., 2014

Hardware Trojan Attacks: Threat Analysis and Countermeasures.
Proc. IEEE, 2014

Guest Editorial Computing in Emerging Technologies (First Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Active defense against counterfeiting attacks through robust antifuse-based on-chip locks.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Robust low-power reconfigurable computing with a variation-aware preferential design approach.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

A non-volatile memory based physically unclonable function without helper data.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Trade-off between energy and quality of service through dynamic operand truncation and fusion.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Hardware trojan attacks in FPGA devices: threat analysis and effective counter measures.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Energy-efficient hardware acceleration through computing in the memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Toward ultralow-power computing at exteme with silicon carbide (SiC) nanoelectromechanical logic.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

CACI: Dynamic Current Analysis Towards Robust Recycled Chip Identification.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis.
IEEE Trans. Computers, 2013

Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution.
IEEE Des. Test, 2013

Ultralow-Power and Robust Embedded Memory for Bioimplantable Microsystems.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Dual-gate silicon carbide (SiC) lateral nanoelectromechanical switches.
Proceedings of the 8th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2013

Nanomechanical non-volatile memory for computing at extreme.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Content-aware encoding for improving energy efficiency in multi-level cell resistive random access memory.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Reconfigurable ECC for adaptive protection of memory.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Secure and Trusted SoC: Challenges and Emerging Solutions.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

RESP: a robust physical unclonable function retrofitted into embedded SRAM array.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Role of power grid in side channel attack and power-grid-aware secure design.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

ScanPUF: Robust ultralow-overhead PUF using scan chain.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Ultralow-Power Implantable Electronics.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Healing of DSP Circuits Under Power Bound Using Post-Silicon Operand Bitwidth Truncation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Introduction to Special Issue on Implantable Electronics.
ACM J. Emerg. Technol. Comput. Syst., 2012

Self-Healing Design in Deep Scaled CMOS Technologies.
J. Circuits Syst. Comput., 2012

Improving IC Security Against Trojan Attacks Through Integration of Security Monitors.
IEEE Des. Test Comput., 2012

Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory.
Proceedings of the 25th International Conference on VLSI Design, 2012

SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation.
Proceedings of the 25th International Conference on VLSI Design, 2012

Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design.
Proceedings of the 25th International Conference on VLSI Design, 2012

Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks.
Proceedings of the 25th International Conference on VLSI Design, 2012

Memory-based computing for performance and energy improvement in multicore architectures.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Implantable ultrasonic dual functional assembly for detection and treatment of anomalous growth.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

Software exploitable hardware Trojans in embedded processor.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache.
IEEE Trans. Computers, 2011

Ultra-Low-Power and Robust Digital-Signal-Processing Hardware for Implantable Neural Interface Microsystems.
IEEE Trans. Biomed. Circuits Syst., 2011

Security Against Hardware Trojan Attacks Using Key-Based Design Obfuscation.
J. Electron. Test., 2011

Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

NEMTronics: Symbiotic integration of nanoelectronic and nanomechanical devices for energy-efficient adaptive computing.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Embedded Software Security through Key-Based Control Flow Obfuscation.
Proceedings of the Security Aspects in Information Technology, 2011

Sequential hardware Trojan: Side-channel aware design and placement.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

TeSR: A robust Temporal Self-Referencing approach for Hardware Trojan detection.
Proceedings of the HOST 2011, 2011

Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Low-power implantable ultrasound imager for online monitoring of tumor growth.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches.
Proceedings of the Design, Automation and Test in Europe, 2011

Multi-level attacks: An emerging security concern for cryptographic hardware.
Proceedings of the Design, Automation and Test in Europe, 2011

MECCA: A Robust Low-Overhead PUF Using Embedded Memory Array.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

2010
Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Low-overhead <i>F</i><sub><i>max</i></sub> calibration at multiple operating points using delay-sensitivity-based path selection.
ACM Trans. Design Autom. Electr. Syst., 2010

<i>A Special Issue on</i> 23rd IEEE International Conference on VLSI Design, Bangalore, India, 3-7 January 2010.
J. Low Power Electron., 2010

Guest Editors' Introduction: Managing Uncertainty through Postfabrication Calibration and Repair.
IEEE Des. Test Comput., 2010

Collaborative Trust: A Novel Paradigm of Trusted Mobile Computing
CoRR, 2010

Special session 11B: Hot topic hardware security: Design, test and verification issues.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Trustworthy computing in a multi-core system using distributed scheduling.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach.
Proceedings of the HOST 2010, 2010

A supply-demand model based scalable energy management system for improved energy utilization efficiency.
Proceedings of the International Green Computing Conference 2010, 2010

Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2010

System level self-healing for parametric yield and reliability improvement under power bound.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

2009
HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A study of asynchronous design methodology for robust CMOS-nano hybrid system design.
ACM J. Emerg. Technol. Comput. Syst., 2009

Low-power hybrid complementary metaloxide- semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping.
IET Comput. Digit. Tech., 2009

Computing with nanoscale memory: Model and architecture.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

A circuit-software co-design approach for improving EDP in reconfigurable frameworks.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Security against hardware Trojan through a novel application of design obfuscation.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Dynamic Evaluation of Hardware Trust.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

Security Through Obscurity: An Approach for Protecting Register Transfer Level Hardware IP.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

Hardware Trojan: Threats and emerging solutions.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

MERO: A Statistical Approach for Hardware Trojan Detection.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

2008
Profit Aware Circuit Design Under Process Variations Considering Speed Binning.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput.
IEEE Trans. Computers, 2008

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique.
J. Electron. Test., 2008

Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Low power design under parameter variations.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Hardware protection and authentication through netlist level obfuscation.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

On-Demand Transparency for Improving Hardware Trojan Detectability.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

On-die CMOS voltage droop detection and dynamiccompensation.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement.
Proceedings of the Design, Automation and Test in Europe, 2008

Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme.
Proceedings of the Design, Automation and Test in Europe, 2008

Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction.
Proceedings of the Design, Automation and Test in Europe, 2008

Reconfigurable computing using content addressable memory for improved performance and resource usage.
Proceedings of the 45th Design Automation Conference, 2008

Collective computing based on swarm intelligence.
Proceedings of the 45th Design Automation Conference, 2008

MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Device-Aware Yield-Centric Dual-V<sub>t</sub> Design Under Parameter Variations in Nanoscale Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Low-Power and testable circuit synthesis using Shannon decomposition.
ACM Trans. Design Autom. Electr. Syst., 2007

Hybridization of CMOS With CNT-Based Nano-Electromechanical Switch for Low Leakage and Robust Circuit Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Process Variations and Process-Tolerant Design.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions.
Proceedings of the 2007 IEEE International Test Conference, 2007

Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Low power FPGA design using hybrid CMOS-NEMS approach.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Tolerance to Small Delay Defects by Adaptive Clock Stretching.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Memory based computation using embedded cache for processor yield and reliability improvement.
Proceedings of the 25th International Conference on Computer Design, 2007

Low-overhead design technique for calibration of maximum frequency at multiple operating points.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Low power synthesis of dynamic logic circuits using fine-grained clock gating.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Speed binning aware design methodology to improve profit under parameter variations.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.
IEEE Trans. Very Large Scale Integr. Syst., 2005

A novel wavelet transform-based transient current analysis for fault detection and localization.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Low-power scan design using first-level supply gating.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Synthesis of application-specific highly efficient multi-mode cores for embedded systems.
ACM Trans. Embed. Comput. Syst., 2005

GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks.
IEEE Trans. Computers, 2005

Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current.
J. Electron. Test., 2005

Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current.
J. Electron. Test., 2005

Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Effectiveness of low power dual-V<sub>t</sub> designs in nano-scale technologies under process parameter variations.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points.
Proceedings of the 10th European Test Symposium, 2005

Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits.
Proceedings of the 2005 Design, 2005

Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies.
Proceedings of the 2005 Design, 2005

A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.
Proceedings of the 2005 Design, 2005

A novel synthesis approach for active leakage power reduction using dynamic supply gating.
Proceedings of the 42nd Design Automation Conference, 2005

Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
DCG: deterministic clock-gating for low-power microprocessor design.
IEEE Trans. Very Large Scale Integr. Syst., 2004

A Technique to Reduce Power and Test Application Time in BIST.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

A Novel Low-Power Scan Design Technique Using Supply Gating.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis.
Proceedings of the 2004 Design, 2004

2003
Deterministic Clock Gating for Microprocessor Power Reduction.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications.
Proceedings of the 2003 Design, 2003

2002
Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Content based image retrieval: related issues using Euler vector.
Proceedings of the 2002 International Conference on Image Processing, 2002

Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis.
Proceedings of the 2002 Design, 2002

A novel wavelet transform based transient current analysis for fault detection and localization.
Proceedings of the 39th Design Automation Conference, 2002

A High Performance IDDQ Testable Cache for Scaled CMOS Technologies.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2000
Topological Routing Amidst Polygonal Obstacles.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999
Design, Simulation and Synthesis of an ASIC for Fractal Image Compression.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999


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