Sudipta Paria

According to our database, Sudipta Paria authored at least 33 papers between 2014 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

CIPHR: Cryptography Inspired IP Protection through Fine-Grain Hardware Redaction.

Aritra Dasgupta, Sudipta Paria, Swarup Bhunia

CoRR, April, 2026

Harnessing the Power of LLMs for Enhancing Hardware Security.

Sudipta Paria, Swarup Bhunia

SN Comput. Sci., February, 2026

Exploring Agentic LLM Paradigms for Hardware Verification across Abstraction Levels.

Sudipta Paria, Swarup Bhunia

Proceedings of the 44th IEEE VLSI Test Symposium, 2026

VTS2026 Contest Publication: TTTC's E.J. McCluskey Best Doctoral Thesis Award.

Luca Benini, Paolo Bernardi, Alberto Bosio, Swarup Bhunia, Riccardo Cantoro, Degang Chen, Krishnendu Chakrabarty, Jayeeta Chaudhuri, Bastien Deveautour, Gabriele Filipponi, Angelo Garofalo, Salvatore Pappalardo, Sudipta Paria, Michael Rogenmoser, Philippe Sauter, Michael Sekyere, Chen Wu

Proceedings of the 44th IEEE VLSI Test Symposium, 2026

Evolving Landscape of Attacks on AI Hardware and Robust Defenses.

Habibur Rahaman, Sudipta Paria, Atri Chatterjee, Swarup Bhunia

Proceedings of the 27th International Symposium on Quality Electronic Design, 2026

CRISP: Platform-Agnostic Unified Reconfigurable Hardware Security Primitive.

Atri Chatterjee, Sudipta Paria, Aritra Dasgupta, Habibur Rahaman, Baibhab Chatterjee, Swarup Bhunia

Proceedings of the 27th International Symposium on Quality Electronic Design, 2026

PROM: Protection against Reverse Engineering Attacks through Programmable Logic Macros.

Pravin Gaikwad, Aritra Dasgupta, Sudipta Paria, Peyman Dehghanzadeh, Jonathan Cruz, Swarup Bhunia

Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2026

COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events.

Mahmudul Hasan, Sudipta Paria, Swarup Bhunia, Tamzidul Hoque

Proceedings of the Design, Automation & Test in Europe Conference, 2026

2025

LATTE: Library Attack for Evaluating Hardware IP Protections Against Reverse Engineering.

Aritra Dasgupta, Sudipta Paria, Christopher Sozio, Swarup Bhunia

IEEE Des. Test, December, 2025

Intelligent Graybox Fuzzing via ATPG-Guided Seed Generation and Submodule Analysis.

Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Swarup Bhunia, Sai Manoj PD

CoRR, September, 2025

LASA: Enhancing SoC Security Verification with LLM-Aided Property Generation.

Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia

CoRR, June, 2025

Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation.

Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta, Atri Chatterjee, Swarup Bhunia

CoRR, May, 2025

SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs.

Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Venkat Nitin Patnala, Swarup Bhunia, Sai Manoj PD

CoRR, April, 2025

Library-Attack: Reverse Engineering Approach for Evaluating Hardware IP Protection.

Aritra Dasgupta, Sudipta Paria, Christopher Sozio, Andrew Lukefahr, Swarup Bhunia

CoRR, January, 2025

HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction.

Aritra Dasgupta, Sudipta Paria, Swarup Bhunia

IACR Cryptol. ePrint Arch., 2025

Towards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon Stages.

Sudipta Paria, Aritra Dasgupta, Swarup Bhunia

Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking.

Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia

Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

LASSO: LLM-Aided Security Property Generation for Assertion-based SoC Verification.

Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia

Proceedings of the 7th ACM/IEEE Symposium on Machine Learning for CAD, 2025

LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency.

Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta, Atri Chatterjee, Swarup Bhunia

Proceedings of the IEEE International Test Conference, 2025

LAMBDA: LLM-Assisted Malicious Bug Detection and Analysis in Hardware Designs.

Sudipta Paria

Proceedings of the IEEE International Test Conference, 2025

FV-PAL: Scalable Formal Verification through Partitioning and LLM-Guided Property Generation.

Sudipta Paria, Aritra Dasgupta, Dinesh Reddy Ankireddy, Prabuddha Chakraborty, Swarup Bhunia

Proceedings of the 43rd IEEE International Conference on Computer Design, 2025

PROFUZZ: Directed Graybox Fuzzing via Module Selection and ATPG-Guided Seed Generation.

Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Swarup Bhunia, Sai Manoj P. D.

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage.

Tanzim Mahfuz, Sudipta Paria, Tasneem Suha, Swarup Bhunia, Prabuddha Chakraborty

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

SPELL: An End-to-End Tool Flow for LLM-Guided Secure SoC Design for Embedded Systems.

Sudipta Paria, Aritra Dasgupta, Swarup Bhunia

IEEE Embed. Syst. Lett., December, 2024

VALIANT: An EDA Flow for Side-Channel Leakage Evaluation and Tailored Protection.

Rajat Sadhukhan, Sayandeep Saha, Sudipta Paria, Swarup Bhunia, Debdeep Mukhopadhyay

IEEE Trans. Computers, February, 2024

Splitting the Secrets: A Cooperative Trust Model for System-on-Chip Designs with Untrusted IPs.

Aritra Dasgupta, Sudipta Paria, Prabuddha Chakraborty, Swarup Bhunia

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

IP Security in Structured ASIC: Challenges and Prospects.

Rasheed Almawzan, Sudipta Paria, Aritra Dasgupta, Kostas Amberiadis, Swarup Bhunia

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement.

Sudipta Paria, Aritra Dasgupta, Swarup Bhunia

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

Navigating SoC Security Landscape on LLM-Guided Paths.

Sudipta Paria, Aritra Dasgupta, Swarup Bhunia

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection.

Sudipta Paria, Pravin Gaikwad, Aritra Dasgupta, Swarup Bhunia

Proceedings of the 33rd IEEE Asian Test Symposium, 2024

2023

DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protection.

Sudipta Paria, Aritra Dasgupta, Swarup Bhunia

CoRR, 2023

DiSPEL: Distributed Security Policy Enforcement for Bus-based SoC.

Sudipta Paria, Swarup Bhunia

CoRR, 2023

2014

Structural analysis and regular expressions based noise elimination from web pages for web content mining.

Amit Dutta, Sudipta Paria, Tanmoy Golui, Dipak K. Kole

Proceedings of the 2014 International Conference on Advances in Computing, 2014