Arjun Rajagopal

According to our database, Arjun Rajagopal authored at least 7 papers between 1993 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS.

Raguram Damodaran, Timothy Anderson, Sanjive Agarwala, Rama Venkatasubramanian, Michael Gill, Dhileep Gopalakrishnan, Anthony M. Hill, Abhijeet Chachad, Dheera Balasubramanian, Naveen Bhoria, Jonathan Tran, Duc Bui, Mujibur Rahman, Shriram Moharil, Matthew Pierson, Steven Mullinnix, Hung Ong, David Thompson, Krishna Gurram, Oluleye Olorode, Nuruddin Mahmood, Jose Flores, Arjun Rajagopal, Soujanya Narnur, Daniel Wu, Alan Hales, Kyle Peavy, Robert Sussman

Proceedings of the 25th International Conference on VLSI Design, 2012

2008

Practical Clock Tree Robustness Signoff Metrics.

Anand Rajaram, Raguram Damodaran, Arjun Rajagopal

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure.

Sanjive Agarwala, Arjun Rajagopal, Anthony M. Hill, Mayur Joshi, Steven Mullinnix, Timothy Anderson, Raguram Damodaran, Lewis Nardini, Paul Wiley, Peter Groves, John Apostol, Michael Gill, Jose Flores, Abhijeet Chachad, Alan Hales, Kai Chirca, Krishna Panda, Rama Venkatasubramanian, Patrick Eyres, Rajasekhar Velamuri, Anand Rajaram, Manjeri Krishnan, Jonathan Nelson, Jose Frade, Mujibur Rahman, Nuruddin Mahmood, Usha Narasimha, Snehamay Sinha, Sridhar Krishnan, William Webster, Duc Bui, Shriram Moharil, Neil Common, Rejitha Nair, Rajesh Ramanujam, Monica Ryan

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

Clock tree design challenges for robust and low power design.

Arjun Rajagopal

Proceedings of the 2006 International Symposium on Physical Design, 2006

2004

A 800 MHz System-on-Chip for Wireless Infrastructure Applications.

Sanjive Agarwala, Paul Wiley, Arjun Rajagopal, Anthony M. Hill, Raguram Damodaran, Lewis Nardini, Tim Anderson, Steven Mullinnix, Jose Flores, Heping Yue, Abhijeet Chachad, John Apostol, Kyle Castille, Usha Narasimha, Tod Wolf, N. S. Nagaraj, Manjeri Krishnan, Luong Nguyen, Todd Kroeger, Mike Gill, Peter Groves, Bill Webster, Joel Graber, Christine Karlovich

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2002

A 600-MHz VLIW DSP.

Sanjive Agarwala, Timothy Anderson, Anthony M. Hill, M. D. Ales, Raguram Damodaran, Paul Wiley, Steven Mullinnix, J. Leach, Anthony Lell, Michael Gill, Arjun Rajagopal, Abhijeet Chachad, M. Agarwala, John Apostol, Manjeri Krishnan, Duc Bui, Quang An, N. S. Nagaraj, Tod Wolf, T. T. Elappuparackal

IEEE J. Solid State Circuits, 2002

1993

A Reconfigurable Arithmetic Processor.

Arjun Rajagopal, Belli Kuttanna, Balaji Janakiraman, Rajarshi Mukherjee, Joy Shetler

Proceedings of the Sixth International Conference on VLSI Design, 1993