Anand Rajaram

According to our database, Anand Rajaram authored at least 16 papers between 2004 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

BufFormer: A Generative ML Framework for Scalable Buffering.

Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, Haoxing Ren

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2011

Robust Chip-Level Clock Tree Synthesis.

Anand Rajaram, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis.

Anand Rajaram, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009

Analysis and optimization of NBTI induced clock skew in gated clock trees.

Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Practical Clock Tree Robustness Signoff Metrics.

Anand Rajaram, Raguram Damodaran, Arjun Rajagopal

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Robust chip-level clock tree synthesis for SOC designs.

Anand Rajaram, David Z. Pan

Proceedings of the 45th Design Automation Conference, 2008

MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks.

Anand Rajaram, David Z. Pan

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure.

Sanjive Agarwala, Arjun Rajagopal, Anthony M. Hill, Mayur Joshi, Steven Mullinnix, Timothy Anderson, Raguram Damodaran, Lewis Nardini, Paul Wiley, Peter Groves, John Apostol, Michael Gill, Jose Flores, Abhijeet Chachad, Alan Hales, Kai Chirca, Krishna Panda, Rama Venkatasubramanian, Patrick Eyres, Rajasekhar Velamuri, Anand Rajaram, Manjeri Krishnan, Jonathan Nelson, Jose Frade, Mujibur Rahman, Nuruddin Mahmood, Usha Narasimha, Snehamay Sinha, Sridhar Krishnan, William Webster, Duc Bui, Shriram Moharil, Neil Common, Rejitha Nair, Rajesh Ramanujam, Monica Ryan

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis.

Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006

Analytical bound for unwanted clock skew due to wire width variation.

Anand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Reducing clock skew variability via crosslinks.

Anand Rajaram, Jiang Hu, Rabi N. Mahapatra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction.

Anand Rajaram, David Z. Pan

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Variation tolerant buffered clock network synthesis with cross links.

Anand Rajaram, David Z. Pan

Proceedings of the 2006 International Symposium on Physical Design, 2006

2005

Improved algorithms for link-based non-tree clock networks for skew variability reduction.

Anand Rajaram, David Z. Pan, Jiang Hu

Proceedings of the 2005 International Symposium on Physical Design, 2005

Practical techniques to reduce skew and its variations in buffered clock networks.

Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004

Reducing clock skew variability via cross links.

Anand Rajaram, Jiang Hu, Rabi N. Mahapatra

Proceedings of the 41th Design Automation Conference, 2004