Artur Balasinski

According to our database, Artur Balasinski authored at least 5 papers between 2000 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

Question: DRC or DfM ? Answer: FMEA and ROI.

Artur Balasinski

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005

DfM for SoC, invited.

Artur Balasinski

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

3.125 Gb/s power efficient line driver with 2-level pre-emphasis and 2 kV HBM ESD protection.

Krzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Sebastian Magierowski, Rafal Dlugosz, Adam Dabrowski

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Design Strategies for ESD Protection in SOC.

Krzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Marek Syrzycki

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

2000

Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Designs.

Valery Axelrad, Nicolas B. Cobb, M. O'Brien, Thuy Do, Tom Donnelly, Yuri Granik, Emile Y. Sahouria, Victor Boksha, Artur Balasinski

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000