Aruna Jayasena

According to our database, Aruna Jayasena authored at least 18 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

SleepWalk: Exploiting Context Switching and Residual Power for Physical Side-Channel Attacks.

Sahan Sanjaya, Aruna Jayasena, Prabhat Mishra

CoRR, July, 2025

Information Leakage Through Physical Layer Supply Voltage Coupling Vulnerability.

Sahan Sanjaya, Aruna Jayasena, Prabhat Mishra

IEEE Trans. Very Large Scale Integr. Syst., June, 2025

FirmWall: Directed Symbolic Execution of Firmware Binaries for Defending Against Unauthorized System Calls.

Aruna Jayasena, Prabhat Mishra

IEEE Trans. Inf. Forensics Secur., 2025

CiseLeaks: Information Leakage Assessment of Cryptographic Instruction Set Extension Prototypes.

Aruna Jayasena, Richard Bachmann, Prabhat Mishra

IEEE Trans. Inf. Forensics Secur., 2025

Formal verification of bioinformatics software using model checking and theorem proving.

Hansika Weerasena, Aruna Jayasena, Christina Boucher, Prabhat Mishra

Briefings Bioinform., 2025

2024

HIVE: Scalable Hardware-Firmware Co-Verification Using Scenario-Based Decomposition and Automated Hint Extraction.

Aruna Jayasena, Prabhat Mishra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

Incremental Concolic Testing of Register-Transfer Level Designs.

Hasini Witharana, Aruna Jayasena, Prabhat Mishra

ACM Trans. Design Autom. Electr. Syst., May, 2024

Directed Test Generation for Hardware Validation: A Survey.

Aruna Jayasena, Prabhat Mishra

ACM Comput. Surv., May, 2024

Design for Trust Utilizing Rareness Reduction.

Aruna Jayasena, Prabhat Mishra

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

EvilCS: An Evaluation of Information Leakage through Context Switching on Security Enclaves.

Aruna Jayasena, Richard Bachmann, Prabhat Mishra

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Scalable Detection of Hardware Trojans Using ATPG-Based Activation of Rare Events.

Aruna Jayasena, Prabhat Mishra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms.

Aruna Jayasena, Emma Andrews, Prabhat Mishra

IEEE Trans. Very Large Scale Integr. Syst., September, 2023

Automated Generation of Security Assertions for RTL Models.

Hasini Witharana, Aruna Jayasena, Andrew Whigham, Prabhat Mishra

ACM J. Emerg. Technol. Comput. Syst., January, 2023

Logic Locking based Trojans: A Friend Turns Foe.

Yuntao Liu, Aruna Jayasena, Prabhat Mishra, Ankur Srivastava

CoRR, 2023

Sequence-Based Incremental Concolic Testing of RTL Models.

Hasini Witharana, Aruna Jayasena, Prabhat Mishra

CoRR, 2023

DETER: Design for Trust utilizing Rareness Reduction.

Aruna Jayasena, Prabhat Mishra

CoRR, 2023

2022

Network-on-Chip Trust Validation Using Security Assertions.

Aruna Jayasena, Binod Kumar, Subodha Charles, Hasini Witharana, Prabhat Mishra

J. Hardw. Syst. Secur., 2022

Efficient Finite State Machine Encoding for Defending Against Laser Fault Injection Attacks.

Aruna Jayasena, Khushboo Rani, Prabhat Mishra

Proceedings of the IEEE 40th International Conference on Computer Design, 2022