Prabhat Mishra

Orcid: 0000-0003-3653-6221

Affiliations:
  • University of Florida, Gainesville, USA


According to our database1, Prabhat Mishra authored at least 225 papers between 2001 and 2024.

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Bibliography

2024
Directed Test Generation for Hardware Validation: A Survey.
ACM Comput. Surv., May, 2024

2023
Scalable Detection of Hardware Trojans Using ATPG-Based Activation of Rare Events.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms.
IEEE Trans. Very Large Scale Integr. Syst., September, 2023

Efficient Detection and Localization of DoS Attacks in Heterogeneous Vehicular Networks.
IEEE Trans. Veh. Technol., May, 2023

Automated Generation of Security Assertions for RTL Models.
ACM J. Emerg. Technol. Comput. Syst., January, 2023

QudCom: Towards Quantum Compilation for Qudit Systems.
CoRR, 2023

Revealing CNN Architectures via Side-Channel Analysis in Dataflow-based Inference Accelerators.
CoRR, 2023

Breaking NoC Anonymity using Flow Correlation Attack.
CoRR, 2023

Logic Locking based Trojans: A Friend Turns Foe.
CoRR, 2023

HIVE: Scalable Hardware-Firmware Co-Verification using Scenario-based Decomposition and Automated Hint Extraction.
CoRR, 2023

Hardware Acceleration of Explainable Artificial Intelligence.
CoRR, 2023

Modeling and Exploration of Gain Competition Attacks in Optical Network-on-Chip Architectures.
CoRR, 2023

quAssert: Automatic Generation of Quantum Assertions.
CoRR, 2023

Sequence-Based Incremental Concolic Testing of RTL Models.
CoRR, 2023

DETER: Design for Trust utilizing Rareness Reduction.
CoRR, 2023

Lightweight Encryption and Anonymous Routing in NoC based SoCs.
CoRR, 2023

Security of Electrical, Optical and Wireless On-Chip Interconnects: A Survey.
CoRR, 2023

Feedback-Based Steering for Quantum State Preparation.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023

Quantum Steering of Surface Error Correcting Codes.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023

Towards Secure Classical-Quantum Systems.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

Dynamic Refinement of Hardware Assertion Checkers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Quantum Measurement Discrimination using Cumulative Distribution Functions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Quantum Data Compression for Efficient Generation of Control Pulses.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Hardware Trojan Detection Using Shapley Ensemble Boosting.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
A Survey on Assertion-based Hardware Verification.
ACM Comput. Surv., January, 2022

Digital Watermarking for Detecting Malicious Intellectual Property Cores in NoC Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Data Perturbation and Recovery of Time Series Gene Expression Data.
IEEE ACM Trans. Comput. Biol. Bioinform., 2022

Hardware-Assisted Malware Detection and Localization Using Explainable Machine Learning.
IEEE Trans. Computers, 2022

Network-on-Chip Trust Validation Using Security Assertions.
J. Hardw. Syst. Secur., 2022

Secure Register Allocation for Trusted Code Generation.
IEEE Embed. Syst. Lett., 2022

Eavesdropping Attack Detection Using Machine Learning in Network-on-Chip Architectures.
IEEE Des. Test, 2022

A Survey of Network-on-Chip Security Attacks and Countermeasures.
ACM Comput. Surv., 2022

Backdoor Attacks on Bayesian Neural Networks using Reverse Distribution.
CoRR, 2022

A Survey on Hardware Vulnerability Analysis Using Machine Learning.
IEEE Access, 2022

Modeling of Noisy Quantum Circuits using Random Matrix Theory.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Efficient Finite State Machine Encoding for Defending Against Laser Fault Injection Attacks.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Speculative Load Forwarding Attack on Modern Processors.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Hardware Acceleration of Explainable Machine Learning.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Design of AI Trojans for Evading Machine Learning-based Detection of Hardware Trojans.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Data Criticality in Multithreaded Applications: An Insight for Many-Core Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Directed Test Generation for Activation of Security Assertions in RTL Models.
ACM Trans. Design Autom. Electr. Syst., 2021

MaxSense: Side-channel Sensitivity Maximization for Trojan Detection Using Statistical Test Patterns.
ACM Trans. Design Autom. Electr. Syst., 2021

Scalable Activation of Rare Triggers in Hardware Trojans by Repeated Maximal Clique Sampling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Scalable Concolic Testing of RTL Models.
IEEE Trans. Computers, 2021

Fast Approximate Spectral Normalization for Robust Deep Neural Networks.
CoRR, 2021

Hardware Acceleration of Explainable Machine Learning using Tensor Processing Units.
CoRR, 2021

Data Criticality in Multi-Threaded Applications: An Insight for Many-Core Systems.
CoRR, 2021

Denial-of-service attack detection using machine learning in network-on-chip architectures.
Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021

Accelerating Spectral Normalization for Enhancing Robustness of Deep Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Lightweight Encryption Using Chaffing and Winnowing with All-or-Nothing Transform for Network-on-Chip Architectures.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

Automated Detection of Spectre and Meltdown Attacks Using Explainable Machine Learning.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

Hardware-Assisted Malware Detection using Machine Learning.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Real-Time Detection and Localization of Denial-of-Service Attacks in Heterogeneous Vehicular Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Quantum Spectral Clustering of Mixed Graphs.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Automated Test Generation for Hardware Trojan Detection using Reinforcement Learning.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Reconfigurable Network-on-Chip Security Architecture.
ACM Trans. Design Autom. Electr. Syst., 2020

Feature-Based Signal Selection for Post-Silicon Debug Using Machine Learning.
IEEE Trans. Emerg. Top. Comput., 2020

Real-Time Detection and Localization of Distributed DoS Attacks in NoC-Based SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

System-on-Chip Security Assertions.
CoRR, 2020

SECTAR: Secure NoC using Trojan Aware Routing.
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020

Securing Network-on-Chip Using Incremental Cryptography.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Lightweight and Trust-Aware Routing in NoC-Based SoCs.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Vulnerability-aware Dynamic Reconfiguration of Partially Protected Caches.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Special Session: Impact of Noise on Quantum Algorithms in Noisy Intermediate-Scale Quantum Systems.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Hardware-Assisted Malware Detection using Explainable Machine Learning.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Test Generation using Reinforcement Learning for Delay-based Side-Channel Analysis.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Automated Test Generation for Trojan Detection using Delay-based Side Channel Analysis.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Lightweight Anonymous Routing in NoC based SoCs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Automated Trigger Activation by Repeated Maximal Clique Sampling.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Automated Test Generation for Activation of Assertions in RTL Models.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Guest Editorial: Special Section on Autonomous Intelligence for Security and Privacy Analytics.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPs.
ACM Trans. Design Autom. Electr. Syst., 2019

Cache Reconfiguration Using Machine Learning for Vulnerability-aware Energy Optimization.
ACM Trans. Embed. Comput. Syst., 2019

Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Directed Test Generation for Validation of Cache Coherence Protocols.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Automated Test Generation for Debugging Multiple Bugs in Arithmetic Circuits.
IEEE Trans. Computers, 2019

Efficient Test Generation for Trojan Detection using Side Channel Analysis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Automated Activation of Multiple Targets in RTL Models using Concolic Testing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Real-time Detection and Localization of DoS Attacks in NoC based SoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

The Metric Matters: The Art of Measuring Trust in Electronics.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Security and Trust Verification of IoT SoCs.
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019

2018
Scalable Test Generation for Trojan Detection Using Side Channel Analysis.
IEEE Trans. Inf. Forensics Secur., 2018

A Survey of Side-Channel Attacks on Caches and Countermeasures.
J. Hardw. Syst. Secur., 2018

Hardware Trojan Detection Using ATPG and Model Checking.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Exploration of Memory and Cluster Modes in Directory-Based Many-Core CMPs.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution.
Proceedings of the IEEE International Test Conference, 2018

Proactive Thermal Management using Memory-based Computing in Multicore Architectures.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

An automated configurable Trojan insertion framework for dynamic trust benchmarks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Directed test generation using concolic testing on RTL models.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Postsilicon Trace Signal Selection Using Machine Learning Techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Editorial.
IEEE Trans. Very Large Scale Integr. Syst., 2017

DyPO: Dynamic Pareto-Optimal Configuration Selection for Heterogeneous MpSoCs.
ACM Trans. Embed. Comput. Syst., 2017

Trace Buffer Attack on the AES Cipher.
J. Hardw. Syst. Secur., 2017

Post-Silicon Validation in the SoC Era: A Tutorial Introduction.
IEEE Des. Test, 2017

Vulnerability-Aware Energy Optimization Using Reconfigurable Caches in Multicore Systems.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

FSM Anomaly Detection Using Formal Analysis.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Automated Debugging of Arithmetic Circuits Using Incremental Gröbner Basis Reduction.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

QUEBS: Qualifying Event Based Search in Concolic Testing for Validation of RTL Models.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Cost-effective analysis of post-silicon functional coverage events.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Trojan localization using symbolic algebra.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Efficient Selection of Trace and Scan Signals for Post-Silicon Debug.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Efficient Resource Constrained Scheduling Using Parallel Structure-Aware Pruning Techniques.
IEEE Trans. Computers, 2016

Test Generation for Hybrid Systems Using Clustering and Learning Techniques.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Automatic RTL-to-Formal Code Converter for IP Security Formal Verification.
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016

Reliability and energy-aware cache reconfiguration for embedded systems.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Scalable SoC trust verification using integrated theorem proving and model checking.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Exploiting transaction level models for observability-aware post-silicon test generation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Automated test generation for Debugging arithmetic circuits.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

MERS: Statistical Test Generation for Side-Channel Analysis based Trojan Detection.
Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, 2016

2015
Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems.
Proceedings of the 28th International Conference on VLSI Design, 2015

Efficient Peak Power Estimation Using Probabilistic Cost-Benefit Analysis.
Proceedings of the 28th International Conference on VLSI Design, 2015

Trace Buffer Attack: Security versus observability study in post-silicon debug.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Variation-aware evaluation of MPSoC task allocation and scheduling strategies using statistical model checking.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Pre-silicon security verification and validation: a formal perspective.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Learning-oriented Property Decomposition for Automated Generation of Directed Tests.
J. Electron. Test., 2014

TECS: Temperature- and Energy-Constrained Scheduling for Multicore Systems.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Scalable Test Generation by Interleaving Concrete and Symbolic Execution.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Layout-aware signal selection in reconfigurable architectures.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

Layout-Aware Selection of Trace Signals for Post-Silicon Debug.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Efficient trace signal selection using augmentation and ILP techniques.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Directed test generation for hybrid systems.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013
RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Bitmask aware compression of NISC control words.
Integr., 2013

Efficient Signal Selection Using Fine-grained Combination of Scan and Trace Buffers.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Tutorial T10: Post - Silicon Validation, Debug and Diagnosis.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Assertion-Based Functional Consistency Checking between TLM and RTL Models.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Proactive thermal management using memory based computing.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Content-aware encoding for improving energy efficiency in multi-level cell resistive random access memory.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Dynamic Selection of Trace Signals for Post-Silicon Debug.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

Branch-and-bound style resource constrained scheduling using efficient structure-aware pruning.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Scalable trace signal selection using machine learning.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012
Energy-Aware Scheduling and Dynamic Reconfiguration in Real-Time Systems.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Directed test generation for validation of multicore architectures.
ACM Trans. Design Autom. Electr. Syst., 2012

Dynamic Cache Reconfiguration for Soft Real-Time Systems.
ACM Trans. Embed. Comput. Syst., 2012

Automatic RTL Test Generation from SystemC TLM Specifications.
ACM Trans. Embed. Comput. Syst., 2012

TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Energy-aware dynamic slack allocation for real-time multitasking systems.
Sustain. Comput. Informatics Syst., 2012

Compression-aware dynamic cache reconfiguration for embedded systems.
Sustain. Comput. Informatics Syst., 2012

Temperature-aware Task Partitioning for Real-Time Scheduling in Embedded Systems.
Proceedings of the 25th International Conference on VLSI Design, 2012

Intra-Task Dynamic Cache Reconfiguration.
Proceedings of the 25th International Conference on VLSI Design, 2012

Constrained signal selection for post-silicon validation.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Memory-based computing for performance and energy improvement in multicore architectures.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Synergistic integration of code encryption and compression in embedded systems.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Automated generation of directed tests for transition coverage in cache coherence protocols.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Decoding-Aware Compression of FPGA Bitstreams.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Property Learning Techniques for Efficient Generation of Directed Tests.
IEEE Trans. Computers, 2011

Energy-aware dynamic reconfiguration algorithms for real-time multitasking systems.
Sustain. Comput. Informatics Syst., 2011

Dynamic Reconfiguration of Two-Level Cache Hierarchy in Real-Time Embedded Systems.
J. Low Power Electron., 2011

Challenges of Rapidly Emerging Consumer Space Multiprocessors.
IEEE Des. Test Comput., 2011

A Brief History of Multiprocessors and EDA.
IEEE Des. Test Comput., 2011

Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models.
IEEE Des. Test Comput., 2011

Efficient trace data compression using statically selected dictionary.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A General Algorithm for Energy-Aware Dynamic Reconfiguration in Multitasking Systems.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Dual Code Compression for Embedded Systems.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Efficient Trace Signal Selection for Post Silicon Validation and Debug.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Efficient combination of trace and scan signals for post silicon validation and debug.
Proceedings of the 2011 IEEE International Test Conference, 2011

Efficient directed test generation for validation of multicore architectures.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Synergistic integration of dynamic cache reconfiguration and code compression in embedded systems.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Decision ordering based property decomposition for functional test generation.
Proceedings of the Design, Automation and Test in Europe, 2011

Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems.
Proceedings of the 48th Design Automation Conference, 2011

2010
Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Functional Test Generation Using Efficient Property Clustering and Learning Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Guest Editorial.
J. Electron. Test., 2010

Efficient test case generation for validation of UML activity diagrams.
Des. Autom. Embed. Syst., 2010

Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Synchronized Generation of Directed Tests Using Satisfiability Solving.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Efficient decision ordering techniques for SAT-based test generation.
Proceedings of the Design, Automation and Test in Europe, 2010

PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme.
Proceedings of the 47th Design Automation Conference, 2010

2009
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation.
ACM Trans. Embed. Comput. Syst., 2009

Functional test generation using design and property decomposition techniques.
ACM Trans. Embed. Comput. Syst., 2009

A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Guest Editor Introduction: Special Issue on Nano/Bio-Inspired Applications and Architectures.
Int. J. Parallel Program., 2009

SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Efficient Placement of Compressed Code for Parallel Decompression.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Efficient Techniques for Directed Test Generation Using Incremental Satisfiability.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Lossless Compression Using Efficient Encoding of Bitmasks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Chairs' welcome message.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Bitmask-based control word compression for NISC architectures.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Generating test programs to cover pipeline interactions.
Proceedings of the 46th Design Automation Conference, 2009

2008
Specification-driven directed test generation for validation of pipelined processors.
ACM Trans. Design Autom. Electr. Syst., 2008

Bitmask-Based Code Compression for Embedded Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Coverage-driven automatic test generation for uml activity diagrams.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A novel test-data compression technique using application-aware bitmask and dictionary selection methods.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Specification-based compaction of directed tests for functional validation of pipelined processors.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

2007
Towards RTL test generation from SystemC TLM specifications.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

An efficient code compression technique using application-aware bitmask and dictionary selection methods.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A Retargetable Software Timing Analyzer Using Architecture Description Language.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs.
ACM Trans. Design Autom. Electr. Syst., 2006

A retargetable framework for instruction-set architecture simulation.
ACM Trans. Embed. Comput. Syst., 2006

Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study.
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

A bitmask-based code compression technique for embedded systems.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Test generation using SAT-based bounded model checking for validation of pipelined processors.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Functional test generation using property decompositions for validation of pipelined processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
A methodology for validation of microprocessors using symbolic simulation.
Int. J. Embed. Syst., 2005

Language-driven Validation of Pipelined Processors using Satisfiability Solvers.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Functional Coverage Driven Test Generation for Validation of Pipelined Processors.
Proceedings of the 2005 Design, 2005

Memory access optimizations in instruction-set simulators.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Functional verification of programmable embedded architectures - a top-down approach.
Springer, ISBN: 978-0-387-26143-0, 2005

2004
Processor-memory coexploration using an architecture description language.
ACM Trans. Embed. Comput. Syst., 2004

Modeling and validation of pipeline specifications.
ACM Trans. Embed. Comput. Syst., 2004

A Top-Down Methodology for Microprocessor Validation.
IEEE Des. Test Comput., 2004

Synthesis-driven Exploration of Pipelined Embedded Processors.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Functional Verification of Pipelined Processors: A Case Study.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Functional Validation of Programmable Architectures.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Graph-Based Functional Test Program Generation for Pipelined Processors.
Proceedings of the 2004 Design, 2004

2003
Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications.
Des. Autom. Embed. Syst., 2003

Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

A Methodology for Validation of Microprocessors using Equivalence Checking.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Instruction set compiled simulation: a technique for fast and flexible instruction set simulation.
Proceedings of the 40th Design Automation Conference, 2003

An efficient retargetable framework for instruction-set simulation.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions.
Proceedings of the Design and Analysis of Distributed Embedded Systems, IFIP 17<sup>th</sup> World Computer Congress, 2002

Automatic functional test program generation for pipelined processors using model checking.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units.
Proceedings of the 2002 Design, 2002

2001
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Functional abstraction driven design space exploration of heterogeneous programmable architectures.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Automatic validation of pipeline specifications.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001


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