Aruna Jayasena

Orcid: 0000-0002-8347-5065

According to our database1, Aruna Jayasena authored at least 12 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Bibliography

2024
Directed Test Generation for Hardware Validation: A Survey.
ACM Comput. Surv., May, 2024

Information Leakage through Physical Layer Supply Voltage Coupling Vulnerability.
CoRR, 2024

Design for Trust Utilizing Rareness Reduction.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
Scalable Detection of Hardware Trojans Using ATPG-Based Activation of Rare Events.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms.
IEEE Trans. Very Large Scale Integr. Syst., September, 2023

Automated Generation of Security Assertions for RTL Models.
ACM J. Emerg. Technol. Comput. Syst., January, 2023

Logic Locking based Trojans: A Friend Turns Foe.
CoRR, 2023

HIVE: Scalable Hardware-Firmware Co-Verification using Scenario-based Decomposition and Automated Hint Extraction.
CoRR, 2023

Sequence-Based Incremental Concolic Testing of RTL Models.
CoRR, 2023

DETER: Design for Trust utilizing Rareness Reduction.
CoRR, 2023

2022
Network-on-Chip Trust Validation Using Security Assertions.
J. Hardw. Syst. Secur., 2022

Efficient Finite State Machine Encoding for Defending Against Laser Fault Injection Attacks.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022


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