Ankur Srivastava

Computer, March, 2024

2023

Security-Aware Resource Binding to Enhance Logic Obfuscation.

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[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Introduction to the Special Issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle.

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[DOI]

ACM J. Emerg. Technol. Comput. Syst., January, 2023

Logic Locking based Trojans: A Friend Turns Foe.

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[DOI]

CoRR, 2023

Low Overhead System-Level Obfuscation through Hardware Resource Sharing.

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[DOI]

Daniel Xing

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Low Power Logic Obfuscation Through System Level Clock Gating.

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[DOI]

Daniel Xing

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

TimingCamouflage+ Decamouflaged.

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[DOI]

Priya Mittu

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

Evaluating the Security of Logic-Locked Probabilistic Circuits.

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[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

DynaMarks: Defending Against Deep Learning Model Extraction Using Dynamic Watermarking.

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[DOI]

CoRR, 2022

A Black-Box Sensitization Attack on SAT-Hard Instances in Logic Obfuscation.

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[DOI]

Isaac McDaniel

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

A Combined Logical and Physical Attack on Logic Obfuscation.

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[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD Tool.

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[DOI]

Jeyavijayan Rajendran

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A Survey on Side-Channel-based Reverse Engineering Attacks on Deep Neural Networks.

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[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

Ising-FPGA: A Spintronics-based Reconfigurable Ising Model Solver.

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[DOI]

ACM Trans. Design Autom. Electr. Syst., 2021

Trace Logic Locking: Improving the Parametric Space of Logic Locking.

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[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Evaluating the Security of Delay-Locked Circuits.

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[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Robust and Attack Resilient Logic Locking with a High Application-Level Impact.

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[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2021

Enhancing Processor Design Obfuscation Through Security-Aware On-Chip Memory and Data Path Design.

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[DOI]

IACR Cryptol. ePrint Arch., 2021

A Resource Binding Approach to Logic Obfuscation.

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[DOI]

IACR Cryptol. ePrint Arch., 2021

Invited: Independent Verification and Validation of Security-Aware EDA Tools and IP.

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[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Keynote: A Disquisition on Logic Locking.

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[DOI]

Nithyashankari Gummidipoondi Jayasankaran

Jeyavijayan Rajendran

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Energy-efficient Design of MTJ-based Neural Networks with Stochastic Computing.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2020

Strong Anti-SAT: Secure and Effective Logic Locking.

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[DOI]

IACR Cryptol. ePrint Arch., 2020

GANRED: GAN-based Reverse Engineering of DNNs via Cache Side-Channel.

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[DOI]

IACR Cryptol. ePrint Arch., 2020

A Survey on Neural Trojans.

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[DOI]

IACR Cryptol. ePrint Arch., 2020

Hardware-Assisted Intellectual Property Protection of Deep Learning Models.

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[DOI]

IACR Cryptol. ePrint Arch., 2020

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.

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[DOI]

CoRR, 2020

DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator.

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[DOI]

IEEE Comput. Archit. Lett., 2020

ObfusGEM: Enhancing Processor Design Obfuscation Through Security-Aware On-Chip Memory and Data Path Design.

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[DOI]

Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

Spintronics-based Reconfigurable Ising Model Architecture.

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[DOI]

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

StatSAT: A Boolean Satisfiability based Attack on Logic-Locked Probabilistic Circuits.

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[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Reducing Timing Side-Channel Information Leakage Using 3D Integration.

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[DOI]

IEEE Trans. Dependable Secur. Comput., 2019

Enhanced Phase-Driven Q-Learning-Based DRM for Multicore Processors.

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[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Anti-SAT: Mitigating SAT Attack on Logic Locking.

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[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

In Situ Stochastic Training of MTJ Crossbars With Machine Learning Algorithms.

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[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2019

Hardware-Software Co-Design Based Obfuscation of Hardware Accelerators.

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[DOI]

IACR Cryptol. ePrint Arch., 2019

Memory Locking: An Automated Approach to Processor Design Obfuscation.

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[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Mitigating Reverse Engineering Attacks on Deep Neural Networks.

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[DOI]

Dana Dachman-Soled

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018

A Combined Optimization-Theoretic and Side- Channel Approach for Attacking Strong Physical Unclonable Functions.

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[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Data Driven Optimizations for MTJ based Stochastic Computing.

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[DOI]

CoRR, 2018

HMCTherm: a cycle-accurate HMC simulator integrated with detailed power and thermal simulation.

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[DOI]

Proceedings of the International Symposium on Memory Systems, 2018

Value-driven Synthesis for Neural Network ASICs.

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[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

In-situ Stochastic Training of MTJ Crossbar based Neural Networks.

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[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

TimingSAT: timing profile embedded SAT attack.

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[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

GPU obfuscation: attack and defense strategies.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Low-Power Clock Tree Synthesis for 3D-ICs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

TSV-Based 3-D ICs: Design Methods and Tools.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Correlation Power Analysis Attack against STT-MRAM Based Cyptosystems.

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[DOI]

IACR Cryptol. ePrint Arch., 2017

Security-Aware 2.5D Integrated Circuit Design Flow Against Hardware IP Piracy.

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[DOI]

Computer, 2017

Power optimizations in MTJ-based Neural Networks through Stochastic Computing.

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[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Introducing TFUE: The trusted foundry and untrusted employee model in IC supply chain security.

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[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Neural Trojans.

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[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Template Attack Based Deobfuscation of Integrated Circuits.

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[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Exploring timing side-channel attacks on path-ORAMs.

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[DOI]

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Design Space Modeling and Simulation for Physically Constrained 3D CPUs.

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[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors.

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[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and Overproduction.

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[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Unlocking the True Potential of 3-D CPUs With Microfluidic Cooling.

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[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Security and Vulnerability Implications of 3D ICs.

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[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2016

On Reverse Engineering-Based Hardware Trojan Detection.

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[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Mitigating SAT Attack on Logic Locking.

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[DOI]

IACR Cryptol. ePrint Arch., 2016

Thermoelectric Codesign of 3-D CPUs and Embedded Microfluidic Pin-Fin Heatsinks.

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[DOI]

IEEE Des. Test, 2016

2.5D/3D Integration Technologies for Circuit Obfuscation.

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[DOI]

Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016

Post-Placement Optimization for Thermal-Induced Mechanical Stress Reduction.

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[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Electromigration-aware placement for 3D-ICs.

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[DOI]

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

An optimization-theoretic approach for attacking physical unclonable functions.

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[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

ECO Based Placement and Routing Framework for 3D FPGAs with Micro-fluidic Cooling.

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[DOI]

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015

Modeling and Layout Optimization for Tapered TSVs.

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[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

TSV Replacement and Shield Insertion for TSV-TSV Coupling Reduction in 3-D Global Placement.

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[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Temperature Tracking: Toward Robust Run-Time Detection of Hardware Trojans.

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[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

3D Integration: New opportunities in defense against cache-timing side-channel attacks.

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[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A security-aware design scheme for better hardware Trojan detection sensitivity.

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[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Electromigration-aware Clock Tree Synthesis for TSV-based 3D-ICs.

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[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Security-Aware Design Flow for 2.5D IC Technology.

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[DOI]

Proceedings of the 5th International Workshop on Trustworthy Embedded Devices, 2015

2014

Statistical Framework for Designing On-Chip Thermal Sensing Infrastructure in Nanoscale Systems.

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[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Optimized Micro-Channel Design for Stacked 3-D-ICs.

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[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs.

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[DOI]

Integr., 2014

On application of one-class SVM to reverse engineering-based hardware Trojan detection.

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[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2014

Unlocking the true potential of 3D CPUs with micro-fluidic cooling.

[BibT_eX]

[DOI]

Donald Yeung

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Gated low-power clock tree synthesis for 3D-ICs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

A Secure Algorithm for Task Scheduling against Side-channel Attacks.

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[DOI]

Proceedings of the 4th International Workshop on Trustworthy Embedded Devices, 2014

2013

Dynamic Thermal Management Under Soft Thermal Constraints.

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[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Thermal-aware sensor scheduling for distributed estimation.

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[DOI]

ACM Trans. Sens. Networks, 2013

Resource-aware architectures for adaptive particle filter based visual target tracking.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

Energy- and Thermal-Aware Video Coding via Encoder/Decoder Workload Balancing.

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[DOI]

ACM Trans. Embed. Comput. Syst., 2013

Improving the Quality of Delay-Based PUFs via Optical Proximity Correction.

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[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Co-design of micro-fluidic heat sink and thermal through-silicon-vias for cooling of three-dimensional integrated circuit.

[BibT_eX]

[DOI]

Avram Bar-Cohen

IET Circuits Devices Syst., 2013

Micro-Fluidic Cooling for Stacked 3D-ICs: Fundamentals, Modeling and Design.

[BibT_eX]

[DOI]

Adv. Comput., 2013

Temperature tracking: an innovative run-time approach for hardware Trojan detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Co-optimization of TSV assignment and micro-channel placement for 3D-ICs.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Thermal stress aware 3D-IC statistical static timing analysis.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Online TSV health monitoring and built-in self-repair to overcome aging.

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[DOI]

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

High performance 3D stacked DRAM processor architectures with micro-fluidic cooling.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Detailed electrical and reliability study of tapered TSVs.

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[DOI]

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

Thermal and Power-Aware Task Scheduling and Data Placement for Storage Centric Datacenters.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Accelerating Gate Sizing Using Graphics Processing Units.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Hybrid 3D-IC Cooling System Using Micro-fluidic Cooling and Thermal TSVs.

[BibT_eX]

[DOI]

Avram Bar-Cohen

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Manipulating Manufacturing Variations for Better Silicon-Based Physically Unclonable Functions.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

TSV-constrained micro-channel infrastructure design for cooling stacked 3D-ICs.

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[DOI]

Proceedings of the International Symposium on Physical Design, 2012

On improving the uniqueness of silicon-based physically unclonable functions via optical proximity correction.

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[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Accurate Temperature Estimation Using Noisy Thermal Sensors for Gaussian and Non-Gaussian Cases.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Unified datacenter power management considering on-chip and air temperature constraints.

[BibT_eX]

[DOI]

Sustain. Comput. Informatics Syst., 2011

Energy-aware and quality-scalable data placement and retrieval for disks in video server environments.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Adaptable architectures for distributed visual target tracking.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Statistical characterization of chip power behavior at post-fabrication stage.

[BibT_eX]

[DOI]