Arvin Shahani

According to our database1, Arvin Shahani authored at least 5 papers between 1997 and 2003.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2003
40-43-Gb/s OC-768 16: 1 MUX/CMU chipset with SFI-5 compliance.
IEEE J. Solid State Circuits, 2003

A 40-43-Gb/s clock and data recovery IC with integrated SFI-5 1: 16 demultiplexer in SiGe technology.
IEEE J. Solid State Circuits, 2003

1998
Low-power dividerless frequency synthesis using aperture phase detection.
IEEE J. Solid State Circuits, 1998

A 115-mW, 0.5-μm CMOS GPS receiver with wide dynamic-range active filters.
IEEE J. Solid State Circuits, 1998

1997
A 12-mW wide dynamic range CMOS front-end for a portable GPS receiver.
IEEE J. Solid State Circuits, 1997


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