C. Patrick Yue

According to our database1, C. Patrick Yue authored at least 43 papers between 1993 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A 42-dB Ω 25-Gb/s CMOS Transimpedance Amplifier With Multiple-Peaking Scheme for Optical Communications.
IEEE Trans. on Circuits and Systems, 2020

2019
A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 0.65V 12-to-16GHz Sub-Sampling PLL with 56.4fsrms Integrated Jitter and -256.4dB FoM.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
EMI-Related Common-Mode (CM) Noise Analysis and Prediction of High-Speed Source-Series Terminated (SST) I/O Driver in System-on-Package (SOP).
IEEE Trans. on Circuits and Systems, 2018

A Full Ka-Band Power Amplifier With 32.9% PAE and 15.3-dBm Power in 65-nm CMOS.
IEEE Trans. on Circuits and Systems, 2018

A 16-GB/S 0-DB Power Back-Off 16-QAM Transmitter at 28 GHZ in 65-NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017
A 60-GHz 4-Gb/s Fully Integrated NRZ-to-QPSK Fiber-Wireless Modulator.
IEEE Trans. on Circuits and Systems, 2017

EMI common-mode (CM) noise suppression from self-calibration of high-speed SST driver using on-chip process monitoring circuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A low-power PAM4 receiver using 1/4-rate sampling decoder with adaptive variable-gain rectification.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

Fully-integrated AMLED micro display system with a hybrid voltage regulator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A 32.9% PAE, 15.3 dBm, 21.6-41.6 GHz power amplifier in 65nm CMOS using coupled resonators.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection.
IEEE Trans. on Circuits and Systems, 2015

An AMLED microdisplay driver SoC with built-in 1.25-Mb/s VLC transmitter.
Proceedings of the Symposium on VLSI Circuits, 2015

A fully integrated IEEE 802.15.7 visible light communication transmitter with on-chip 8-W 85% efficiency boost LED driver.
Proceedings of the Symposium on VLSI Circuits, 2015

20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 60GHz 4Gb/s fully integrated NRZ-to-QPSK modulator SoC for backhaul links in fiber-wireless networks.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
A 26-28-Gb/s Full-Rate Clock and Data Recovery Circuit With Embedded Equalizer in 65-nm CMOS.
IEEE Trans. on Circuits and Systems, 2014

Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection.
J. Solid-State Circuits, 2014

A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizer.
Proceedings of the Symposium on VLSI Circuits, 2014

Towards indoor localization using Visible Light Communication for consumer electronic devices.
Proceedings of the 2014 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2014

A 41-mW 30-Gb/s CMOS optical receiver with digitally-tunable cascaded equalization.
Proceedings of the ESSCIRC 2014, 2014

2013
A ±0.5% Precision On-Chip Frequency Reference With Programmable Switch Array for Crystal-Less Applications.
IEEE Trans. on Circuits and Systems, 2013

A 13.56MHz fully integrated 1X/2X active rectifier with compensated bias current for inductively powered devices.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV+ ESD protection by co-design.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A 25-Gb/s 32.1-dB CMOS limiting amplifier for integrated optical receivers.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Wireless power link design using silicon-embedded inductors for brain-machine interface.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

The evolution of fabless IC industry in China: Past, present, and future.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Welcome from the general chairs.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A near-threshold, multi-node, wireless body area sensor network powered by RF energy harvesting.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2009
A 1.1V 150GHz amplifier with 8dB gain and +6dBm saturated output power in standard digital 65nm CMOS using dummy-prefilled microstrip lines.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 1-mW 12-Gb/s continuous-time adaptive passive equalizer in 90-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Modeling of triple-well isolation and the loading effects on circuits up to 50 GHz.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A two-tone test method for continuous-time adaptive equalizers.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2005
A low-power, 20-Gb/s continuous-time adaptive passive equalizer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
On-Chip Interconnect Inductance - Friend or Foe (Invited).
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Design of a 10GHz clock distribution network using coupled standing-wave oscillators.
Proceedings of the 40th Design Automation Conference, 2003

1999
RF Passive IC Components.
Proceedings of the VLSI Handbook., 1999

Design Strategy of On-Chip Inductors for Highly Integrated RF Systems.
Proceedings of the 36th Conference on Design Automation, 1999

1993
Improved universal MOSFET electron mobility degradation models for circuit simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993


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