Ashok Narasimhan

According to our database1, Ashok Narasimhan authored at least 10 papers between 2004 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2010
Variability Aware Low-Power Delay Optimal Buffer Insertion for Global Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009
Variation aware low power buffered interconnect design.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008
A low power and low area active clock deskewing technique for sub-90nm technologies.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

2007
Impact of Variability on Clock Skew in H-tree Clock Networks.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006
Energy Conservation in Sensor Networks through Selective Node Activation.
Proceedings of the 2006 International Symposium on a World of Wireless, 2006

A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005
A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A High-Performance Router Design for VDSM NoCs.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

2004
Leakage aware SER reduction technique for UDSM logic circuits.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004


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