Ashok Srivastava

Orcid: 0000-0002-0357-2130

According to our database1, Ashok Srivastava authored at least 52 papers between 1996 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2021
Evaluating the Performances of Memristor, FinFET, and Graphene TFET in VLSI Circuit Design.
Proceedings of the 11th IEEE Annual Computing and Communication Workshop and Conference, 2021

High Q-Factor Graphene-Based Inductor CMOS LC Voltage Controlled Oscillator for PLL Applications.
Proceedings of the 34th IEEE Canadian Conference on Electrical and Computer Engineering, 2021

2020
0.4 mW, 0.27 pJ/bit true random number generator using jitter, metastability and current starved topology.
IET Circuits Devices Syst., 2020

A 250 MHz-to-1.6 GHz Phase Locked Loop Design in Hybrid FinFET-Memristor Technology.
Proceedings of the 11th IEEE Annual Ubiquitous Computing, 2020

2019
Long Short-Term Memory Network Design for Analog Computing.
ACM J. Emerg. Technol. Comput. Syst., 2019

Novel, Low-power ECRL-CMOS Interface Circuit.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

AI for Small Businesses and Consumers: Applications and Innovations.
Proceedings of the 25th ACM SIGKDD International Conference on Knowledge Discovery & Data Mining, 2019

2018
qSwitch: Dynamical Off-Chip Bandwidth Allocation Between Local and Remote Accesses.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Multiple Input Floating Gate Based Arithmetic Logic Unit with a Feedback Loop for Digital Calibration.
J. Low Power Electron., 2018

Calibration method to reduce the error in logarithmic conversion with its circuit implementation.
IET Circuits Devices Syst., 2018

Building robust classifiers through generation of confident out of distribution examples.
CoRR, 2018

Improving robustness of classifiers by training against live traffic.
CoRR, 2018

Evaluation of Four Power Gating Schemes Applied to ECRL Adiabatic Logic.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
Modeling of Joule Heating Induced Effects in Multiwall Carbon Nanotube Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Using Switchable Pins to Increase Off-Chip Bandwidth in Chip-Multiprocessors.
IEEE Trans. Parallel Distributed Syst., 2017

A novel switchable pin method for regulating power in chip-multiprocessor.
Integr., 2017

Guest editorial - Special issue on hardware assisted techniques for IoT and bigdata applications.
Integr., 2017

Foreword to the Applied Data Science: Invited Talks Track at KDD-2017.
Proceedings of the 23rd ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, Halifax, NS, Canada, August 13, 2017

Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
Large-Scale Machine Learning at Verizon: Theory and Applications.
Proceedings of the 22nd ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, 2016

A Low-Cost Mixed Clock Generator for High Speed Adiabatic Logic.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Modeling of Graphene Nanoribbon Tunnel Field Effect Transistor in Verilog-A for Digital Circuit Design.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

Width-Dependent Characteristics of Graphene Nanoribbon Field Effect Transistor for High Frequency Applications.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

2015
Powering Up Dark Silicon: Mitigating the Limitation of Power Delivery via Dynamic Pin Switching.
IEEE Trans. Emerg. Top. Comput., 2015

Scaling Effects on Static Metrics and Switching Attributes of Graphene Nanoribbon FET for Emerging Technology.
IEEE Trans. Emerg. Top. Comput., 2015

An Algorithm Used in a Power Monitor to Mitigate Dark Silicon on VLSI Chip.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Circuit Implementation of Switchable Pins in Chip Multiprocessor.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Clocked Adiabatic XOR and XNOR CMOS Gates Design Based on Graphene Nanoribbon Complementary Field Effect Transistors.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Characterization of SWCNT Bundle Based VLSI Interconnect with Self-heating Induced Scatterings.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
Low Power-Variable Resolution Analog-to-Digital Converter.
J. Low Power Electron., 2014

Characterization of MWCNT VLSI Interconnect with Self-Heating Induced Scatterings.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Increasing off-chip bandwidth in multi-core processors with switchable pins.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2013
Classification and Adaptive Novel Class Detection of Feature-Evolving Data Streams.
IEEE Trans. Knowl. Data Eng., 2013

A novel graphene nanoribbon field effect transistor for integrated circuit design.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012
A Programmable Oversampling CMOS Delta-Sigma Analog-to-Digital Converter for Low-Power Interface Electronics.
J. Low Power Electron., 2012

CMOS Phase-Locked Loop Circuits and Hot Carrier Effects.
J. Low Power Electron., 2012

CMOS LC voltage controlled oscillator design using multiwalled and single-walled carbon nanotube wire inductors.
ACM J. Emerg. Technol. Comput. Syst., 2012

Top-10 Data Mining Case Studies.
Int. J. Inf. Technol. Decis. Mak., 2012

Analysis of Virtual Sensors for Predicting Aircraft Fuel Consumption.
Proceedings of the Infotech@Aerospace 2012, 2012

Testing of Trusted CMOS Data Converters.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

2011
Δ<i>I<sub>DDQ</sub></i> Testing of a CMOS Digital-to-Analog Converter Considering Process Variation Effects.
Circuits Syst., 2011

Switchable PLL Frequency Synthesizer and Hot Carrier Effects.
Circuits Syst., 2011

2010
A model for carbon nanotube interconnects.
Int. J. Circuit Theory Appl., 2010

Hot carrier effects on CMOS phase-locked loop frequency synthesizers.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009
Stable and Efficient Gaussian Process Calculations.
J. Mach. Learn. Res., 2009

2007
Hot Carrier Effects in Wireless Communication Systems Built on Short-Channel MOSFETs.
IEEE Trans. Wirel. Commun., 2007

2006
OFDM performance analysis in the phase noise arising from the hot-carrier effect.
IEEE Trans. Consumer Electron., 2006

Sensitivity of single-carrier QAM systems to phase noise arising from the hot-carrier effect.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2006

2005
Phase noise analysis for ICI self-cancellation coded OFDM with short-channel synchronization devices.
Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November, 2005

2003
Quaternary to binary bit conversion CMOS integrated circuit design using multiple-input floating gate MOSFETS.
Integr., 2003

1999
Influence of BJT Transit Frequency Limit Relation to MOSFET Parameters on the Switching Speed of BiCMOS Digital Circuits.
VLSI Design, 1999

1996
Improved time series segmentation using gated experts with simulated annealing.
Proceedings of International Conference on Neural Networks (ICNN'96), 1996


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