Manish Goswami

According to our database1, Manish Goswami authored at least 34 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
Design and Analysis of Low-Voltage, MOS-only Bandgap Reference Circuit.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

2022
A Differential LNA Architecture with Improved Figure of Merit Using 40 nm UMC CMOS Technology for mmWave Band Receiver Applications.
Wirel. Pers. Commun., 2022

Design of a Low-Voltage Charge-Sensitive Preamplifier Interfaced with Piezoelectric Tactile Sensor for Tumour Detection.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

A 14 nm Single-Ended Schmitt Trigger SRAM Cell for Improved SNM & Delay.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

Design of Hexagonal Oscillator for True Random Number Generation.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
Design of Ultra-Low Power High-Q Single Ended Active Inductors for IF BPF of Receiver Frontend Using 130 nm BiCMOS Technology.
Wirel. Pers. Commun., 2021

Mechanical strain and bias-stress compensated, 6T-1C pixel circuit for flexible AMOLED displays.
Microelectron. J., 2021

A Current Tunable Mixed Mode ZC-CCTAs Based Resistor Less Universal Filter.
J. Circuits Syst. Comput., 2021

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications.
J. Circuits Syst. Comput., 2021

Design of True Random Number Generator Using Fingerprint as an Entropy Source and Its Implementation in S-Box.
J. Circuits Syst. Comput., 2021

Design and Analysis of SRAM cell using Body Bias Controller for Low Power Applications.
Circuits Syst. Signal Process., 2021

2020
Design of a voltage-programmed <i>V</i> <sub>TH</sub> compensating pixel circuit for AMOLED displays using diode-connected a-IGZO TFT.
IET Circuits Devices Syst., 2020

0.4 mW, 0.27 pJ/bit true random number generator using jitter, metastability and current starved topology.
IET Circuits Devices Syst., 2020

Design of Transceiver at 865-867 MHz Band using UMC 180 nm CMOS Technology.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Opto-Radio Noise based True Random Number Generator.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Design of SRAM cell using Voltage Lowering and Stacking Techniques for Low Power Applications.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2018
A 2.4 GHz Low Power Low Phase-Noise Enhanced FOM VCO for RF Applications Using 180 nm CMOS Technology.
Wirel. Pers. Commun., 2018

Six-bit, reusable comparator stage-based asynchronous binary-search SAR ADC using smart switching network.
IET Circuits Devices Syst., 2018

A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Modified Tent Map Based Design for True Random Number Generator.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Analysis of modulation schemes for Bluetooth-LE module for Internet-of-Things (IoT) applications.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

2017
Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC.
J. Circuits Syst. Comput., 2017

Fabrication of flexible sensors for electrodermal activity measurement.
Proceedings of the 29th International Conference on Microelectronics, 2017

2016
A Modified SRAM Based Low Power Memory Design.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Low power multi threshold 7T SRAM cell.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

2015
An Improved Dynamic Latch Based Comparator for 8-Bit Asynchronous SAR ADC.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
Low Power-Variable Resolution Analog-to-Digital Converter.
J. Low Power Electron., 2014

Optimized Architecture for AES.
IACR Cryptol. ePrint Arch., 2014

A Low Power 8-Bit Asynchronous SAR ADC Design Using Charge Scaling DAC.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

2013
An Improvement in Media Discovery Service Using Name Spotting.
Proceedings of the 2013 IEEE International Symposium on Multimedia, 2013

4-6 Bit Variable Resolution ADC.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

A 5-bit 1.5 GS/s ADC using reduced comparator architecture.
Proceedings of the 8th International Design and Test Symposium, 2013

Comparator-multiplexer based 6 bit 1.4GSPS low power ADC.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

2009
Novel Current-mode Waveform Generator with Independent Frequency and Amplitude Control.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009


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