Ashwin Ramachandran

According to our database, Ashwin Ramachandran authored at least 12 papers between 2005 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

ReFoRCE: A Text-to-SQL Agent with Self-Refinement, Format Restriction, and Column Exploration.

Minghang Deng, Ashwin Ramachandran, Canwen Xu, Lanxiang Hu, Zhewei Yao, Anupam Datta, Hao Zhang

CoRR, February, 2025

Charting the Design Space of Neural Graph Representations for Subgraph Matching.

Vaibhav Raj, Indradyumna Roy, Ashwin Ramachandran, Soumen Chakrabarti, Abir De

Proceedings of the Thirteenth International Conference on Learning Representations, 2025

2024

Text-to-SQL Calibration: No Need to Ask - Just Rescale Model Probabilities.

Ashwin Ramachandran, Sunita Sarawagi

CoRR, 2024

Iteratively Refined Early Interaction Alignment for Subgraph Matching based Graph Retrieval.

Ashwin Ramachandran, Vaibhav Raj, Indradyumna Roy, Soumen Chakrabarti, Abir De

Proceedings of the Advances in Neural Information Processing Systems 38: Annual Conference on Neural Information Processing Systems 2024, 2024

2022

A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS.

Yusang Chun, Mohamed Megahed, Ashwin Ramachandran, Tejasvi Anand

IEEE J. Solid State Circuits, 2022

2020

An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS.

Ashwin Ramachandran, Yusang Chun, Mohamed Megahed, Tejasvi Anand

IEEE J. Solid State Circuits, 2020

2019

Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping.

Ashwin Ramachandran, Arun Natarajan, Tejasvi Anand

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Switched Capacitor Multiple Input Single Output Energy Harvester (Solar + Piezo) Achieving 74.6% Efficiency With Simultaneous MPPT.

Abhishekh Devaraj, Mohamed Megahed, Yutao Liu, Ashwin Ramachandran, Tejasvi Anand

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS.

Yusang Chun, Ashwin Ramachandran, Tejasvi Anand

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018

A 0.5-to-0.9V, 3-to-16Gb/s, 1.6-to-3.1pJ/b wireline transceiver equalizing 27dB loss at 10Gb/s with clock-domain encoding using integrated pulse-width modulation (iPWM) in 65nm CMOS.

Ashwin Ramachandran, Tejasvi Anand

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS.

Ashwin Ramachandran, Arun Natarajan, Tejasvi Anand

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2005

Providing intelligent help across applications in dynamic user and environment contexts.

Ashwin Ramachandran, R. Michael Young

Proceedings of the 10th International Conference on Intelligent User Interfaces, 2005