Tejasvi Anand

According to our database1, Tejasvi Anand authored at least 44 papers between 2011 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
A 3.5-mV Input Single-Inductor Self-Starting Boost Converter With Loss-Aware MPPT for Efficient Autonomous Body-Heat Energy Harvesting.
IEEE J. Solid State Circuits, 2021

A Machine Learning Inspired Transceiver with ISI-Resilient Data Encoding: Hybrid-Ternary Coding + 2-Tap FFE + CTLE + Feature Extraction and Classification for 44.7dB Channel Loss in 7.3pJ/bit.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A 27 Gb/s 5.39 pJ/bit 8-ary Modulated Wireline Transceiver Using Pulse Width and Amplitude Modulation Achieving 9.5 dB SNR Improvement over PAM-8.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020
A 951-fs<sub>rms</sub> Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator.
IEEE J. Solid State Circuits, 2020

An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020

An ISI-Resilient Data Encoding for Equalizer-Free Wireline Communication - Dicode Encoding and Error Correction for 24.2-dB Loss With 2.56 pJ/bit.
IEEE J. Solid State Circuits, 2020

2019
Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Switched Capacitor Multiple Input Single Output Energy Harvester (Solar + Piezo) Achieving 74.6% Efficiency With Simultaneous MPPT.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Integrated Cold Start of a Boost Converter at 57 mV Using Cross-Coupled Complementary Charge Pumps and Ultra-Low-Voltage Ring Oscillator.
IEEE J. Solid State Circuits, 2019

A Stochastic Wireline Communication System.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A Sub 1μW Switched Source + Capacitor Architecture Free of Top/Bottom Plate Parasitic Switching Loss Achieving Peak Efficiency of 80.66% at a Regulated 1.8V Output in 180nm.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 13.6-16Gb/s Wireline Transceiver with Dicode Encoding and Sequence Detection Decoding for Equalizing 24.2dB with 2.56pJ/bit in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 3.5mV Input, 82% Peak Efficiency Boost Converter with Loss-Optimized MPPT and 50mV Integrated Cold-Start for Thermoelectric Energy Harvesting.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects.
IEEE J. Solid State Circuits, 2018

A Fully Decoupled LC Tank VCO Topology for Amplitude Boosted Low Phase Noise Operation.
IEEE J. Solid State Circuits, 2018

A 0.5-to-0.9V, 3-to-16Gb/s, 1.6-to-3.1pJ/b wireline transceiver equalizing 27dB loss at 10Gb/s with clock-domain encoding using integrated pulse-width modulation (iPWM) in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Fully-integrated 57 mV cold start of a thermoelectric energy harvester using a cross-coupled complementary charge pump.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver.
IEEE J. Solid State Circuits, 2017

29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition.
IEEE J. Solid State Circuits, 2016

A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity.
IEEE J. Solid State Circuits, 2016

2015
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method.
IEEE J. Solid State Circuits, 2015

Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers.
IEEE J. Solid State Circuits, 2015

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC.
IEEE J. Solid State Circuits, 2015

A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links.
IEEE J. Solid State Circuits, 2015

A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links.
IEEE J. Solid State Circuits, 2015

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

A self-referenced VCO-based temperature sensor with 0.034°C/mV supply sensitivity in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS.
IEEE J. Solid State Circuits, 2014

A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links.
IEEE J. Solid State Circuits, 2014

A 75dB DR 50MHz BW 3<sup>rd</sup> order CT-ΔΣ modulator using VCO-based integrators.
Proceedings of the Symposium on VLSI Circuits, 2014

A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter.
Proceedings of the Symposium on VLSI Circuits, 2014

A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement.
Proceedings of the Symposium on VLSI Circuits, 2014

A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC.
Proceedings of the Symposium on VLSI Circuits, 2014

8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A power-scalable RF CMOS receiver for 2.4 GHz Wireless Sensor Network applications.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
A scalable network port scan detection system on FPGA.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011


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