Yusang Chun

According to our database, Yusang Chun authored at least 8 papers between 2019 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET.

Henry Park, Mohammed Abdullatif, Ehung Chen, Ahmed Elmallah, Qaiser Nehal, Miguel Gandara, Tsz-Bin Liu, Amr Khashaba, Joonyeong Lee, Chih-Yi Kuan, Dhinessh Ramachandran, Ruey-Bo Sun, Atharav Atharav, Yusang Chun, Mantian Zhang, Deng-Fu Weng, Chung-Hsien Tsai, Chen-Hao Chang, Chia-Sheng Peng, Sheng-Tsung Hsu, Tamer A. Ali

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS.

Yusang Chun, Mohamed Megahed, Ashwin Ramachandran, Tejasvi Anand

IEEE J. Solid State Circuits, 2022

2021

A Machine Learning Inspired Transceiver with ISI-Resilient Data Encoding: Hybrid-Ternary Coding + 2-Tap FFE + CTLE + Feature Extraction and Classification for 44.7dB Channel Loss in 7.3pJ/bit.

Zhiping Wang, Mohamed Megahed, Yusang Chun, Tejasvi Anand

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A 27 Gb/s 5.39 pJ/bit 8-ary Modulated Wireline Transceiver Using Pulse Width and Amplitude Modulation Achieving 9.5 dB SNR Improvement over PAM-8.

Mohamed Megahed, Yusang Chun, Zhiping Wang, Tejasvi Anand

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020

An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS.

Ashwin Ramachandran, Yusang Chun, Mohamed Megahed, Tejasvi Anand

IEEE J. Solid State Circuits, 2020

An ISI-Resilient Data Encoding for Equalizer-Free Wireline Communication - Dicode Encoding and Error Correction for 24.2-dB Loss With 2.56 pJ/bit.

Yusang Chun, Tejasvi Anand

IEEE J. Solid State Circuits, 2020

2019

A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS.

Yusang Chun, Ashwin Ramachandran, Tejasvi Anand

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 13.6-16Gb/s Wireline Transceiver with Dicode Encoding and Sequence Detection Decoding for Equalizing 24.2dB with 2.56pJ/bit in 65nm CMOS.

Yusang Chun, Tejasvi Anand

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019