Ashwin Ramachandran
Orcid: 0000-0002-2321-3397
According to our database1,
Ashwin Ramachandran
authored at least 8 papers
between 2005 and 2022.
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Bibliography
2022
A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS.
IEEE J. Solid State Circuits, 2022
2020
An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020
2019
Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A Switched Capacitor Multiple Input Single Output Energy Harvester (Solar + Piezo) Achieving 74.6% Efficiency With Simultaneous MPPT.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
A 0.5-to-0.9V, 3-to-16Gb/s, 1.6-to-3.1pJ/b wireline transceiver equalizing 27dB loss at 10Gb/s with clock-domain encoding using integrated pulse-width modulation (iPWM) in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2005
Providing intelligent help across applications in dynamic user and environment contexts.
Proceedings of the 10th International Conference on Intelligent User Interfaces, 2005