Atif Raza Jafri

Orcid: 0000-0001-7475-9317

According to our database1, Atif Raza Jafri authored at least 23 papers between 2009 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Auto implementation of parallel hardware architecture for Aho-Corasick algorithm.
Des. Autom. Embed. Syst., 2022

2021
Hardware Implementation of Overlap-Save-Based Fading Channel Emulator.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A systematic review of scalable hardware architectures for pattern matching in network security.
Comput. Electr. Eng., 2021

2020
A 4-Stage Pipelined Architecture for Point Multiplication of Binary Huff Curves.
J. Circuits Syst. Comput., 2020

Exploration of Hardware Architectures for String Matching Algorithms in Network Intrusion Detection Systems.
Proceedings of the IAIT 2020: The 11th International Conference on Advances in Information Technology, 2020

2019
Erratum: Flexible Architectures for Cryptographic Algorithms - A Systematic Literature Review.
J. Circuits Syst. Comput., 2019

Flexible Architectures for Cryptographic Algorithms - A Systematic Literature Review.
J. Circuits Syst. Comput., 2019

Throughput/area optimised pipelined architecture for elliptic curve crypto processor.
IET Comput. Digit. Tech., 2019

2018
FPGA Implementation of UFMC Based Baseband Transmitter: Case Study for LTE 10MHz Channelization.
Wirel. Commun. Mob. Comput., 2018

ACryp-Proc: Flexible Asymmetric Crypto Processor for Point Multiplication.
IEEE Access, 2018

Rapid Prototyping of Parameterized Rotated and Cyclic Q Delayed Constellations Demapper.
Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018

2017
Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Towards an Optimized Architecture for Unified Binary Huff Curves.
J. Circuits Syst. Comput., 2017

Hardware Complexity Reduction in Universal Filtered Multicarrier Transmitter Implementation.
IEEE Access, 2017

High-Throughput and Area-Efficient Rotated and Cyclic Q Delayed Constellations Demapper for Future Wireless Standards.
IEEE Access, 2017

2016
Efficient Hardware Implementation of Ultralightweight RFID Mutual Authentication Protocol.
J. Circuits Syst. Comput., 2016

A New Ultralightweight RFID Mutual Authentication Protocol: SASI Using Recursive Hash.
Int. J. Distributed Sens. Networks, 2016

Comparative analysis of flexible cryptographic implementations.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

2011
Parallel MIMO Turbo Equalization.
IEEE Commun. Lett., 2011

2010
Rapid design and prototyping of universal soft demapper.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
ASIP-Based Universal Demapper for Multiwireless Standards.
IEEE Embed. Syst. Lett., 2009

Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear Equalizer.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications.
Proceedings of the Design, Automation and Test in Europe, 2009


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