Michel Jézéquel

According to our database1, Michel Jézéquel authored at least 84 papers between 1995 and 2020.

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Bibliography

2020
Low-Complexity Angle-Domain MIMO NOMA System with partial channel state information for MmWave Communications.
CoRR, 2020

Multi-User Digital Beamforming Based on Path Angle Information for mm-Wave MIMO Systems.
Proceedings of the 24th International ITG Workshop on Smart Antennas, 2020

Joint SDMA and Power-Domain NOMA System for Multi-User Mm-Wave Communications.
Proceedings of the 16th International Wireless Communications and Mobile Computing Conference, 2020

2019
Budget Restricted Incremental Learning with Pre-Trained Convolutional Neural Networks and Binary Associative Memories.
J. Signal Process. Syst., 2019

Computational Complexity Reduction of MMSE-IC MIMO Turbo Detection.
J. Circuits Syst. Comput., 2019

Efficient Hardware Implementation of Incremental Learning and Inference on Chip.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Performance Evaluation of Linear Precoding mmWave Multi-User MIMO Systems with NYUSIM Channel Simulator.
Proceedings of the 2nd IEEE Middle East and North Africa COMMunications Conference, 2019

2018
Transfer Incremental Learning using Data Augmentation.
CoRR, 2018

2017
Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Efficient quantization and fixed-point representation for MIMO turbo-detection and turbo-demapping.
EURASIP J. Embed. Syst., 2017

Incremental learning on chip.
Proceedings of the 2017 IEEE Global Conference on Signal and Information Processing, 2017

2015
NISC-Based Soft-Input-Soft-Output Demapper.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014
Soft Error Detection and Correction Technique for Radiation Hardening Based on C-element and BICS.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Design and prototyping flow of NISC-based flexible MIMO turbo-equalizer.
Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014

2013
Analysis of the Convergence Process by EXIT Charts for Parallel Implementations of Turbo Decoders.
IEEE Commun. Lett., 2013

Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

Study of a cosmic ray impact on combinatorial logic circuits of an 8bit SAR ADC in 65nm CMOS technology.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Muller C-element based Decoder (MCD): A decoder against transient faults.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Efficient NISI compensation technique for a low-cost satellite video receiver.
Proceedings of IEEE International Conference on Communications, 2013

Statically-scheduled application-specific processor design: a case-study on MMSE MIMO equalization.
Proceedings of the Design, Automation and Test in Europe, 2013

Parameterized area-efficient multi-standard turbo decoder.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
On the Convergence Speed of Turbo Demodulation With Turbo Decoding.
IEEE Trans. Signal Process., 2012

Complexity adaptive iterative receiver performing TBICM-ID-SSD.
EURASIP J. Adv. Signal Process., 2012

A contribution to the reduction of the dynamic power dissipation in the turbo decoder.
Ann. des Télécommunications, 2012

A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

Compensating the high power amplifier nonlinearity for a DVB-S2 system.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

A space-time redundancy technique for embedded stochastic error correction.
Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

Adaptive complexity MIMO turbo receiver applying turbo demodulation.
Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

Adapted scheduling of QC-LDPC decoding for multistandard receivers.
Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

Architecture efficiency of application-specific processors: A 170Mbit/s 0.644mm<sup>2</sup> multi-standard turbo decoder.
Proceedings of the 2012 International Symposium on System on Chip, 2012

An LDPC decoding method for fault-tolerant digital logic.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Complexity reduction of shuffled parallel iterative demodulation with turbo decoding.
Proceedings of the 19th International Conference on Telecommunications, 2012

High speed low complexity radix-16 Max-Log-MAP SISO decoder.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Multi-standard trellis-based FEC decoder.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture.
J. Signal Process. Syst., 2011

A Self-Powered Telemetry System to Estimate the Postoperative Instability of a Knee Implant.
IEEE Trans. Biomed. Eng., 2011

Parallel MIMO Turbo Equalization.
IEEE Commun. Lett., 2011

Reducing the number of iterations in iterative demodulation with turbo decoding.
Proceedings of the 19th International Conference on Software, 2011

Hardware efficiency versus error probability in unreliable computation.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Area and throughput optimized ASIP for multi-standard turbo decoding.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

A low complexity stopping criterion for reducing power consumption in turbo decoders.
Proceedings of the Design, Automation and Test in Europe, 2011

A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Scaling of analog LDPC decoders in sub-100 nm CMOS processes.
Integr., 2010

Parallelism Efficiency in Convolutional Turbo Decoding.
EURASIP J. Adv. Signal Process., 2010

Power consumption analysis and energy efficient optimization for turbo decoder implementation.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

Rapid design and prototyping of universal soft demapper.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A new single-error correction scheme based on self-diagnosis residue number arithmetic.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2009
High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping.
J. Signal Process. Syst., 2009

From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2009

ASIP-Based Universal Demapper for Multiwireless Standards.
IEEE Embed. Syst. Lett., 2009

Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear Equalizer.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Design of an Iterative Receiver for Linearly Precoded MIMO Systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Decoding a Family of Dense Codes using the Sum-Product Algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
A highly parallel Turbo Product Code decoder without interleaving resource.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

On the higher efficiency of parallel Reed-Solomon turbo-decoding.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder.
Proceedings of the 45th Design Automation Conference, 2008

2007
Semi-Iterative Analog Turbo Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Energy Efficient Turbo Decoder with Reduced State Metric Quantization.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Towards Gb/s turbo decoding of product code onto an FPGA device.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Design, Implementation and Prototyping of a Flexible Architecture Dedicated to Block Turbo Decoding.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Efficient architecture for Reed Solomon block turbo code.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Semi-iterative analog turbo decoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

ASIP-based multiprocessor SoC design for simple and double binary turbo decoding.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Design of Three-Dimensional Multiple Slice Turbo Codes.
EURASIP J. Adv. Signal Process., 2005

Foreword / Éditorial.
Ann. des Télécommunications, 2005

On Multiple Slice Turbo Codes.
Ann. des Télécommunications, 2005

. Analog slice turbo decoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Synthèse d'architecture pour la réalisation comportementale de l'algorithme MAP pour Turbo Décodeur.
Ann. des Télécommunications, 2004

Designing good permutations for turbo codes: towards a single model.
Proceedings of IEEE International Conference on Communications, 2004

2002
Application of the error impulse method in the design of high-order turbo coded modulation.
Proceedings of the 2002 IEEE Information Theory Workshop, 2002

Computing the minimum distance of linear codes by the error impulse method.
Proceedings of the Global Telecommunications Conference, 2002

2001
Turbocodes: Une technique qui se diffuse.
Ann. des Télécommunications, 2001

Turbo codes: A wide-spreading technique.
Ann. des Télécommunications, 2001

The advantages of non-binary turbo codes.
Proceedings of the 2001 IEEE Information Theory Workshop, 2001

1999
Multiple parallel concatenation of circular recursive systematic convolutional (Crsc ) codes.
Ann. des Télécommunications, 1999

1995
Iterative correction of intersymbol interference: Turbo-equalization.
Eur. Trans. Telecommun., 1995


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