Amer Baghdadi

Yasser Mohanna

Youssef Atat

Des. Autom. Embed. Syst., 2021

Low Complexity Non-binary Turbo Decoding based on the Local-SOVA Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Topics in Coding, 2021

2020

Overlap-Save FBMC Receivers.

[BibT_eX]

[DOI]

François Leduc-Primeau

IEEE Trans. Wirel. Commun., 2020

Memristive Computational Memory Using Memristor Overwrite Logic (MOL).

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

FPGA based design and prototyping of efficient 5G QC-LDPC channel decoding.

[BibT_eX]

[DOI]

Proceedings of the International Workshop on Rapid System Prototyping, 2020

Memristor Overwrite Logic (MOL) for Energy-Efficient In-Memory DNN.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Computational Complexity Reduction of MMSE-IC MIMO Turbo Detection.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2019

Crossbar Memory Architecture Performing Memristor Overwrite Logic.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

MRL Crossbar-Based Full Adder Design.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018

Novel UF-OFDM Transmitter: Significant Complexity Reduction Without Signal Approximation.

[BibT_eX]

[DOI]

IEEE Trans. Veh. Technol., 2018

Networked Power-Gated MRAMs for Memory-Based Computing.

[BibT_eX]

[DOI]

Jean-Philippe Diguet

Naoya Onizawa

Martha Johanna Sepúlveda

Takahiro Hanyu

IEEE Trans. Very Large Scale Integr. Syst., 2018

Design and Evaluation of a Novel Short Prototype Filter for FBMC/OQAM Modulation.

[BibT_eX]

[DOI]

IEEE Access, 2018

Rapid Prototyping of Parameterized Rotated and Cyclic Q Delayed Constellations Demapper.

[BibT_eX]

[DOI]

Muhammad Waqas

Muhammad Najam-ul-Islam

Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018

NISC Design Experience of Flexible Architectures for Digital Communication Applications.

[BibT_eX]

[DOI]

Ali Chamas Al Ghouwayel

Proceedings of the 2018 International Conference on Computer and Applications (ICCA), 2018

A Block FBMC Receiver Designed for Short Filters.

[BibT_eX]

[DOI]

François Leduc-Primeau

Proceedings of the 2018 IEEE International Conference on Communications, 2018

2017

Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD.

[BibT_eX]

[DOI]

Muhammad Najam-ul-Islam

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Efficient quantization and fixed-point representation for MIMO turbo-detection and turbo-demapping.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2017

Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2017

High-Throughput and Area-Efficient Rotated and Cyclic Q Delayed Constellations Demapper for Future Wireless Standards.

[BibT_eX]

[DOI]

Muhammad Waqas

Muhammad Najam-ul-Islam

IEEE Access, 2017

Reduced complexity FPGA implementation for UF-OFDM frequency domain transmitter.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

NoC-MRAM architecture for memory-based computing: Database-search case study.

[BibT_eX]

[DOI]

Martha Johanna Sepúlveda

Y. Akgul

Vincent Gripon

Takahiro Hanyu

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Flexible hardware platform for demonstrating new 5G waveform candidates.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Microelectronics, 2017

Towards memristor-based reconfigurable FFT architecture.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Microelectronics, 2017

2016

A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Low-Complexity Pipelined Architecture for FBMC/OQAM Transmitter.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

2015

NISC-Based Soft-Input-Soft-Output Demapper.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders.

[BibT_eX]

[DOI]

Carlo Condo

Guido Masera

Circuits Syst. Signal Process., 2015

Caasper: providing accessible FPGA-acceleration over the network.

[BibT_eX]

[DOI]

Valentin Mena Morales

Yahia Brakni

Pierre-Henri Horrein

Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015

2014

Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding.

[BibT_eX]

[DOI]

Carlo Condo

Guido Masera

IET Commun., 2014

Design and prototyping flow of NISC-based flexible MIMO turbo-equalizer.

[BibT_eX]

[DOI]

Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014

UWB-IR digital baseband architecture for IEEE 802.15.6 wireless BAN.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Energy-efficient FPGA implementation for binomial option pricing using OpenCL.

[BibT_eX]

[DOI]

Valentin Mena Morales

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture.

[BibT_eX]

[DOI]

Michael Hübner

Guy Gogniat

Jean-Philippe Diguet

Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Flexible and efficient architecture design for MIMO MMSE-IC linear turbo-equalization.

[BibT_eX]

[DOI]

Proceedings of the Third International Conference on Communications and Information Technology, 2013

Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study.

[BibT_eX]

[DOI]

Carlo Condo

Guido Masera

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Statically-scheduled application-specific processor design: a case-study on MMSE MIMO equalization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Parameterized area-efficient multi-standard turbo decoder.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation.

[BibT_eX]

[DOI]

VLSI Design, 2012

On the Convergence Speed of Turbo Demodulation With Turbo Decoding.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2012

Complexity adaptive iterative receiver performing TBICM-ID-SSD.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2012

FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding.

[BibT_eX]

[DOI]

Jean-Noel Bazin

Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Adaptive complexity MIMO turbo receiver applying turbo demodulation.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

Architecture efficiency of application-specific processors: A 170Mbit/s 0.644mm<sup>2</sup> multi-standard turbo decoder.

[BibT_eX]

[DOI]

Rachid Al-Khayat

Proceedings of the 2012 International Symposium on System on Chip, 2012

Complexity reduction of shuffled parallel iterative demodulation with turbo decoding.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Telecommunications, 2012

2011

On chip interconnects for multiprocessor turbo decoding architectures.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2011

Parallel MIMO Turbo Equalization.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2011

Reducing the number of iterations in iterative demodulation with turbo decoding.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Software, 2011

Area and throughput optimized ASIP for multi-standard turbo decoding.

[BibT_eX]

[DOI]

Rachid Al-Khayat

Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

A low complexity stopping criterion for reducing power consumption in turbo decoders.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding.

[BibT_eX]

[DOI]

Rachid Al-Khayat

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Parallelism Efficiency in Convolutional Turbo Decoding.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2010

Power consumption analysis and energy efficient optimization for turbo decoder implementation.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

Rapid design and prototyping of universal soft demapper.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

ASIP-Based Universal Demapper for Multiwireless Standards.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2009

FPGA-based Radar Signal Processing for Automotive Driver Assistance System.

[BibT_eX]

[DOI]

Jean Saad

Frantz Bodereau

Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear Equalizer.

[BibT_eX]

[DOI]

Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

High-Level System Modeling for Rapid HW/SW Architecture Exploration.

[BibT_eX]

[DOI]

Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder.

[BibT_eX]

[DOI]

Hazem Moussa

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder.

[BibT_eX]

[DOI]

Hazem Moussa

Proceedings of the 45th Design Automation Conference, 2008

2007

Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference.

[BibT_eX]

[DOI]

Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

ASIP-based multiprocessor SoC design for simple and double binary turbo decoding.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip.

[BibT_eX]

[DOI]

Nacer-Eddine Zergainoh

Ahmed Amine Jerraya

Int. J. Embed. Syst., 2005

2004

A generic architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip.

[BibT_eX]

[DOI]

Nacer-Eddine Zergainoh

Ahmed Amine Jerraya

Ann. des Télécommunications, 2004

An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004

An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2003

Towards SoC Validation Through Prototyping: A Systematic Approach Based on Reconfigurable Platform.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2003

Embedded Application Prototyping on a Communication-Restricted Reconfigurable.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

2002

Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des applications spécifiques = methods and tools for multiprocessor systems on chip, hardware/software co-designExploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoC. (Exploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoC).

[BibT_eX]

[DOI]

PhD thesis, 2002

Exploration de l'espace des solutions architecturales dans le codesign.

[BibT_eX]

[DOI]