Aurélien Alacchi

Orcid: 0000-0002-4486-413X

According to our database1, Aurélien Alacchi authored at least 7 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023

Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

2022
Programmable Local Clock SET Filtering for SEE-Resistant FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021
Smart-Redundancy: An Alternative SEU/SET Mitigation Method for FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs.
IEEE Micro, 2020

2019
A Study on Switch Block Patterns for Tileable FPGA Routing Architectures.
Proceedings of the International Conference on Field-Programmable Technology, 2019

OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019


  Loading...