Pierre-Emmanuel Gaillardon

According to our database1, Pierre-Emmanuel Gaillardon authored at least 136 papers between 2009 and 2020.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs.
IEEE Micro, 2020

Exact Benchmark Circuits for Logic Synthesis.
IEEE Des. Test, 2020

SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

A RRAM-based FPGA for Energy-efficient Edge Computing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A Scalable Mixed Synthesis Framework for Heterogeneous Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Distributed Low-Cost Pollution Monitoring Platform.
IEEE Internet Things J., 2019

Accelerating Inference on Binary Neural Networks with Digital RRAM Processing.
Proceedings of the VLSI-SoC: New Technology Enabler, 2019

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors.
Proceedings of the VLSI-SoC: New Technology Enabler, 2019

Functionality Enhanced Memories for Edge-AI Embedded Systems.
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019

GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Wire-Aware Architecture and Dataflow for CNN Accelerators.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

A Study on Switch Block Patterns for Tileable FPGA Routing Architectures.
Proceedings of the International Conference on Field-Programmable Technology, 2019

A Recursive Approach to Partially Blind Calibration of a Pollution Sensor Network.
Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Scalable Boolean Methods in a Modern Synthesis Flow.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Rebooting Our Computing Models.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Memory Effects in Multi-terminal Solid State Devices and Their Applications.
Proceedings of the Handbook of Memristor Networks., 2019

A Taxonomy and Evaluation Framework for Memristive Logic.
Proceedings of the Handbook of Memristor Networks., 2019

2018
Guest Editorial Memristive-Device-Based Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Logic Synthesis for RRAM-Based In-Memory Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Post-P&R Performance and Power Analysis for RRAM-Based FPGAs.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

An Efficient Adder Architecture with Three- Independent-Gate Field-Effect Transistors.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

Emerging reconfigurable nanotechnologies: can they support future electronics?
Proceedings of the International Conference on Computer-Aided Design, 2018

Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors.
Proceedings of the 76th Device Research Conference, 2018

Practical challenges in delivering the promises of real processing-in-memory machines.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Towards high-performance polarity-controllable FETs with 2D materials.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers.
IEEE Trans. Emerg. Top. Comput., 2017

Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Exact Synthesis of Majority-Inverter Graphs and Its Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

A PLiM Computer for the Internet of Things.
Computer, 2017

Memristive logic: A framework for evaluation and comparison.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Low-power multiplexer designs using three-independent-gate field effect transistors.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Optimization opportunities in RRAM-based FPGA architectures.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Physical Design Considerations of One-level RRAM-based Routing Multiplexers.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

RM3 based logic synthesis (Special session paper).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An efficient electronic measurement interface for memristive biosensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Enabling exact delay synthesis.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Wave pipelining for majority-based beyond-CMOS technologies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Endurance management for resistive Logic-In-Memory computing architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A novel basis for logic rewriting.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Multi-level logic benchmarks: An exactness study.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A Study on the Programming Structures for RRAM-Based FPGA Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Majority-Inverter Graph: A New Paradigm for Logic Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Sound and Complete Axiomatization of Majority-n Logic.
IEEE Trans. Computers, 2016

A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.
ACM J. Emerg. Technol. Comput. Syst., 2016

Emerging Technology-Based Design of Primitives for Hardware Security.
ACM J. Emerg. Technol. Comput. Syst., 2016

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Inversion optimization in Majority-Inverter Graphs.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications.
Proceedings of the 17th Latin-American Test Symposium, 2016

Notes on Majority Boolean Algebra.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Digital, analog and RF design opportunities of three-independent-gate transistors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Optimizing Majority-Inverter Graphs with functional hashing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

The Programmable Logic-in-Memory (PLiM) computer.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

An MIG-based compiler for programmable logic-in-memory architectures.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Majority-based synthesis for nanotechnologies.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells.
IEEE Trans. Very Large Scale Integr. Syst., 2015

New Logic Synthesis as Nanotechnology Enabler.
Proc. IEEE, 2015

A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems.
ACM J. Emerg. Technol. Comput. Syst., 2015

NEM relay design with biconditional binary decision diagrams.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

A study on buffer distribution for RRAM-based FPGA routing structures.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A fast pruning technique for low-power inexact Circuit design.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Exploiting Circuit Duality to Speed up SAT.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Reversible Logic Synthesis via Biconditional Binary Decision Diagrams.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

FPGA-SPICE: A simulation-based power estimation framework for FPGAs.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Reliable and high performance STT-MRAM architectures based on controllable-polarity devices.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Accurate power analysis for near-Vt RRAM-based FPGA.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

A surface potential and current model for polarity-controllable silicon nanowire FETs.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Fault modeling in controllable polarity silicon nanowire circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A ultra-low-power FPGA based on monolithically integrated RRAMs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Multiple Independent Gate FETs: How many gates do we need?
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2014

Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Novel configurable logic block architecture exploiting controllable-polarity transistors.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

3D technologies for reconfigurable architectures.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Novel grid-based power routing scheme for regular controllable-polarity FET arrangements.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A high-performance low-power near-Vt RRAM-based FPGA.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Pattern-based FPGA logic block and clustering algorithm.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A new basic logic structure for data-path computation (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Majority Logic Synthesis for Spin Wave Technology.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Advanced system on a chip design based on controllable-polarity FETs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

An efficient manipulation package for Biconditional Binary Decision Diagrams.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Data compression via logic synthesis.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Efficient arithmetic logic gates using double-gate silicon nanowire FETs.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

SATSoT: A methodology to map controllable-polarity devices on a regular fabric using SAT.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study.
Proceedings of the 14th Latin American Test Workshop, 2013

Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

3.5-D integration: A case study.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A fast TCAD-based methodology for Variation analysis of emerging nano-devices.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs.
Proceedings of the Design, Automation and Test in Europe, 2013

Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits.
Proceedings of the Design, Automation and Test in Europe, 2013

Towards structured ASICs using polarity-tunable Si nanowire transistors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

GMS: Generic memristive structure for non-volatile FPGAs.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

2011
Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method.
ACM J. Emerg. Technol. Comput. Syst., 2011

Using OxRRAM memories for improving communications of reconfigurable FPGA architectures.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Ultra-fine grain FPGAs: A granularity study.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Evaluation of a crossbar multiplexer in a lithography-based nanowire technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Can we go towards true 3-D architectures?
Proceedings of the 48th Design Automation Conference, 2011

2010
Reducing transistor count in clocked standard cells with ambipolar double-gate FETs.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Emerging memory technologies for reconfigurable routing in FPGA architecture.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Phase-change-memory-based storage elements for configurable logic.
Proceedings of the International Conference on Field-Programmable Technology, 2010

2009
Emerging Technologies and Nanoscale Computing Fabrics.
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009

Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

Mapping method of reconfigurable cell matrices based on nanoscale devices using inter-stage fixed interconnection scheme.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Reconfigurable nanoscale logic cells : a comparison study.
Proceedings of the 16th IEEE International Conference on Electronics, 2009


  Loading...