Pierre-Emmanuel Gaillardon
Orcid: 0000-0003-3634-3999
According to our database1,
Pierre-Emmanuel Gaillardon
authored at least 175 papers
between 2009 and 2024.
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Bibliography
2024
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024
2023
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
ACM Trans. Reconfigurable Technol. Syst., September, 2023
IEEE Trans. Very Large Scale Integr. Syst., August, 2023
Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023
FlowTune: End-to-End Automatic Logic Optimization Exploration via Domain-Specific Multiarmed Bandit.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report.
CoRR, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023
2022
University of Utah AirU Pollution Monitoring Network - Salt Lake City UT - 2019-07-26 - 2021-05-14.
Dataset, January, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit.
CoRR, 2022
An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
An Open-source Three-Independent-Gate FET Standard Cell Library for Mixed Logic Synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2022
2021
multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures.
ACM J. Emerg. Technol. Comput. Syst., 2021
IEEE Des. Test, 2021
A 12-pA Resolution Sigma Delta ADC Topology for Chemiresistive Sensor-Based Applications.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
A First Approach in Using Super-Steep-Subthreshold-Slope Field-Effect Transistors in Ultra-Low Power Analog Design.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
A Novel High-Gain Amplifier Circuit Using Super-Steep-Subthreshold-Slope Field-Effect Transistors.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs.
Proceedings of the ISPD '21: International Symposium on Physical Design, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021
2020
IEEE Micro, 2020
Proceedings of the VLSI-SoC: Design Trends, 2020
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Proceedings of the VLSI-SoC: New Technology Enabler, 2019
A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the VLSI-SoC: New Technology Enabler, 2019
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the International Conference on Field-Programmable Technology, 2019
Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019
LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Handbook of Memristor Networks., 2019
Proceedings of the Handbook of Memristor Networks., 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
An Efficient Adder Architecture with Three- Independent-Gate Field-Effect Transistors.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors.
Proceedings of the 76th Device Research Conference, 2018
Practical challenges in delivering the promises of real processing-in-memory machines.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Emerg. Top. Comput., 2017
Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
ACM J. Emerg. Technol. Comput. Syst., 2016
ACM J. Emerg. Technol. Comput. Syst., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications.
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems.
ACM J. Emerg. Technol. Comput. Syst., 2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Reliable and high performance STT-MRAM architectures based on controllable-polarity devices.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
A surface potential and current model for polarity-controllable silicon nanowire FETs.
Proceedings of the 45th European Solid State Device Research Conference, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2014
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
Novel configurable logic block architecture exploiting controllable-polarity transistors.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014
Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Novel grid-based power routing scheme for regular controllable-polarity FET arrangements.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
SATSoT: A methodology to map controllable-polarity devices on a regular fabric using SAT.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study.
Proceedings of the 14th Latin American Test Workshop, 2013
Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs.
Proceedings of the Design, Automation and Test in Europe, 2013
Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
2011
Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method.
ACM J. Emerg. Technol. Comput. Syst., 2011
Using OxRRAM memories for improving communications of reconfigurable FPGA architectures.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 48th Design Automation Conference, 2011
2010
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010
Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the International Conference on Field-Programmable Technology, 2010
2009
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009
Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009
Mapping method of reconfigurable cell matrices based on nanoscale devices using inter-stage fixed interconnection scheme.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009