Xifan Tang

Ramesh Karri

IEEE Trans. Very Large Scale Integr. Syst., October, 2023

A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA Design.

[BibT_eX]

[DOI]

Ganesh Gore

Abdul Khader Thalakkattu Moosa

IEEE Trans. Very Large Scale Integr. Syst., August, 2023

2022

ALICE: an automatic design flow for eFPGA redaction.

[BibT_eX]

[DOI]

Chiara Muscari Tomajoli

Luca Collini

Jitendra Bhandari

Benjamin Tan

Ramesh Karri

Christian Pilato

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs.

[BibT_eX]

[DOI]

Ganesh Gore

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

Smart-Redundancy: An Alternative SEU/SET Mitigation Method for FPGAs.

[BibT_eX]

[DOI]

Aurélien Alacchi

Abdul Khader Thalakkattu Moosa

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Exploring eFPGA-based Redaction for IP Protection.

[BibT_eX]

[DOI]

Jitendra Bhandari

Ramesh Karri

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Taping out an FPGA in 24 hours with OpenFPGA: The SOFA Project.

[BibT_eX]

[DOI]

Ganesh Gore

Grant Brown

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs.

[BibT_eX]

[DOI]

IEEE Micro, 2020

A RRAM-based FPGA for Energy-efficient Edge Computing.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A Scalable Mixed Synthesis Framework for Heterogeneous Networks.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Accelerating Inference on Binary Neural Networks with Digital RRAM Processing.

[BibT_eX]

[DOI]

João Vieira

Yasir Mahmood Qureshi

Proceedings of the VLSI-SoC: New Technology Enabler, 2019

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories.

[BibT_eX]

[DOI]

João Vieira

Yasir Mahmood Qureshi

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

A Study on Switch Block Patterns for Tileable FPGA Routing Architectures.

[BibT_eX]

[DOI]

Aurélien Alacchi

Proceedings of the International Conference on Field-Programmable Technology, 2019

LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018

Post-P&R Performance and Power Analysis for RRAM-Based FPGAs.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

2017

Circuit Design, Architecture and CAD for RRAM-based FPGAs.

[BibT_eX]

[DOI]

PhD thesis, 2017

A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2017

Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Optimization opportunities in RRAM-based FPGA architectures.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Physical Design Considerations of One-level RRAM-based Routing Multiplexers.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

A Study on the Programming Structures for RRAM-Based FPGA Architectures.

[BibT_eX]

[DOI]

Gain Kim

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells.

[BibT_eX]

[DOI]

Gain Kim

IEEE Trans. Very Large Scale Integr. Syst., 2015

A study on buffer distribution for RRAM-based FPGA routing structures.

[BibT_eX]

[DOI]

Somayyeh Rahimian Omam

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

FPGA-SPICE: A simulation-based power estimation framework for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Accurate power analysis for near-Vt RRAM-based FPGA.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

A ultra-low-power FPGA based on monolithically integrated RRAMs.

[BibT_eX]

[DOI]

Jury Sandrini

Maxime Thammasack

Somayyeh Rahimian Omam

Davide Sacchetto

Yusuf Leblebici

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs.

[BibT_eX]

[DOI]

Jian Zhang

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Novel configurable logic block architecture exploiting controllable-polarity transistors.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs.

[BibT_eX]

[DOI]

Jian Zhang

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A high-performance low-power near-Vt RRAM-based FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Pattern-based FPGA logic block and clustering algorithm.

[BibT_eX]

[DOI]