Ayan Palchaudhuri

According to our database, Ayan Palchaudhuri authored at least 25 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation.

Ayan Palchaudhuri, Anindya Sundar Dhar

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2022

FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion.

Ayan Palchaudhuri, Digvijay Anand, Anindya Sundar Dhar

J. Parallel Distributed Comput., 2022

2021

Design Automation for Tree-based Nearest Neighborhood-aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion.

Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar

ACM Trans. Design Autom. Electr. Syst., 2021

Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support.

Ayan Palchaudhuri, Anindya Sundar Dhar

J. Parallel Distributed Comput., 2021

2020

Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables.

Ayan Palchaudhuri, Anindya Sundar Dhar

J. Electron. Test., 2020

Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion.

Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability.

Ayan Palchaudhuri, Anindya Sundar Dhar

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019

Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies.

Ayan Palchaudhuri, Anindya Sundar Dhar

J. Parallel Distributed Comput., 2019

Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations.

Ayan Palchaudhuri, Anindya Sundar Dhar

J. Electron. Test., 2019

VLSI Architectures for Jacobi Symbol Computation.

Ayan Palchaudhuri, Anindya Sundar Dhar

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation.

Ayan Palchaudhuri, Anindya Sundar Dhar

Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2018

High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization.

Ayan Palchaudhuri, Anindya Sundar Dhar

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Redundant Binary to Two's Complement Converter on FPGAs Through Fabric Aware Scan Based Encoding Approach for Fault Localization Support.

Ayan Palchaudhuri, Anindya Sundar Dhar

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAs.

Ayan Palchaudhuri, Anindya Sundar Dhar

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017

Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs.

Ayan Palchaudhuri, Amrit Anand Amresh, Anindya Sundar Dhar

J. Cell. Autom., 2017

Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations.

Ayan Palchaudhuri, Anindya Sundar Dhar

J. Electron. Test., 2017

Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs.

Ayan Palchaudhuri, Anindya Sundar Dhar

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs.

Ayan Palchaudhuri, Anindya Sundar Dhar

Proceedings of the 24th IEEE International Conference on High Performance Computing, 2017

2016

Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs.

Ayan Palchaudhuri, Anindya Sundar Dhar

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

High performance bit-sliced pipelined comparator tree for FPGAs.

Ayan Palchaudhuri, Anindya Sundar Dhar

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015

Automated Design of High Performance Integer Arithmetic Cores on FPGA.

Ayan Palchaudhuri, Rajat Subhra Chakraborty, Durga Prasad Sahoo

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

A Fabric Component Based Approach to the Architecture and Design Automation of High-Performance Integer Arithmetic Circuits on FPGA.

Ayan Palchaudhuri, Rajat Subhra Chakraborty

Proceedings of the Computational Intelligence in Digital and Network Designs and Applications, 2015

2014

Highly Compact Automated Implementation of Linear CA on FPGAs.

Ayan Palchaudhuri, Rajat Subhra Chakraborty, Mohammad Salman, Sreemukh Kardas, Debdeep Mukhopadhyay

Proceedings of the Cellular Automata, 2014

2013

Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream.

Rajat Subhra Chakraborty, Indrasish Saha, Ayan Palchaudhuri, Gowtham Kumar Naik

IEEE Des. Test, 2013

2012

Effect of Malicious Hardware Logic on Circuit Reliability.

Sanjay Burman, Ayan Palchaudhuri, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay, Pranav Singh

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012