Durga Prasad Sahoo

Orcid: 0000-0002-5959-518X

According to our database1, Durga Prasad Sahoo authored at least 23 papers between 2013 and 2019.

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Bibliography

2019
The Interpose PUF: Secure PUF Design against State-of-the-art Machine Learning Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

A 0.16pJ/bit recurrent neural network based PUF for enhanced machine learning attack resistance.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Fault-Tolerant Implementations of Physically Unclonable Functions on FPGA.
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019

2018
A Multiplexer-Based Arbiter PUF Composition with Enhanced Reliability and Security.
IEEE Trans. Computers, 2018

A 0.16pJ/bit Recurrent Neural Network Based PUF for Enhanced Machine Learning Atack Resistance.
CoRR, 2018

Trustworthy proofs for sensor data using FPGA based physically unclonable functions.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Security Analysis of Arbiter PUF and Its Lightweight Compositions Under Predictability Test.
ACM Trans. Design Autom. Electr. Syst., 2017

MXPUF: Secure PUF Design against State-of-the-art Modeling Attacks.
IACR Cryptol. ePrint Arch., 2017

Side Channel Evaluation of PUF-Based Pseudorandom Permutation.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Fault Tolerant Implementations of Delay-based Physically Unclonable Functions on FPGA.
IACR Cryptol. ePrint Arch., 2016

Architectural Bias: a Novel Statistical Metric to Evaluate Arbiter PUF Variants.
IACR Cryptol. ePrint Arch., 2016

An Efficient and Scalable Modeling Attack on Lightweight Secure Physically Unclonable Function.
IACR Cryptol. ePrint Arch., 2016

2015
A Novel Memristor-Based Hardware Security Primitive.
ACM Trans. Embed. Comput. Syst., 2015

A Case of Lightweight PUF Constructions: Cryptanalysis and Machine Learning Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A novel memristor based physically unclonable function.
Integr., 2015

Tutorial T7: Physically Unclonable Function: A Promising Security Primitive for Internet of Things.
Proceedings of the 28th International Conference on VLSI Design, 2015

Towards Ideal Arbiter PUF Design on Xilinx FPGA: A Practitioner's Perspective.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Automated Design of High Performance Integer Arithmetic Cores on FPGA.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Efficient attacks on robust ring oscillator PUF with enhanced challenge-response set.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Cryptanalysis of Composite PUFs (Extended abstract-invited talk).
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

Lightweight and Secure PUFs: A Survey (Invited Paper).
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2014

Composite PUF: A new design paradigm for Physically Unclonable Functions on FPGA.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

2013
Design of low area-overhead ring oscillator PUF with large challenge space.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013


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