Anindya Sundar Dhar

According to our database1, Anindya Sundar Dhar authored at least 72 papers between 1992 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
On Fast and Exact Computation of Error Metrics in Approximate LSB Adders.
IEEE Trans. Very Large Scale Integr. Syst., 2020

SIBAM - Sign Inclusive Broken Array Multiplier Design for Error Tolerant Applications.
IEEE Trans. Circuits Syst., 2020

Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables.
J. Electron. Test., 2020

Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019
CORDIC-Based VLSI Architectures of Running DFT with Refreshing Mechanism.
J. Signal Process. Syst., 2019

Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Triple transistor based triple modular redundancy with embedded voter circuit.
Microelectron. J., 2019

Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies.
J. Parallel Distributed Comput., 2019

Improved VLSI architecture for triangular windowed sliding DFT based on CORDIC algorithm.
IET Circuits Devices Syst., 2019

Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations.
J. Electron. Test., 2019

VLSI Architectures for Jacobi Symbol Computation.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Defect Tolerant Majority Voter Design Using Triple Transistor Redundancy.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2018
An Efficient VLSI Architecture for Computation of Discrete Fractional Fourier Transform.
J. Signal Process. Syst., 2018

Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Reliable VLSI Architecture Design Using Modulo-Quad-Transistor Redundancy Method.
Circuits Syst. Signal Process., 2018

CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation.
Circuits Syst. Signal Process., 2018

High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Redundant Binary to Two's Complement Converter on FPGAs Through Fabric Aware Scan Based Encoding Approach for Fault Localization Support.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Triple transistor based fault tolerance for resource constrained applications.
Microelectron. J., 2017

Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs.
J. Cell. Autom., 2017

High-performance VLSI architectures for M-PSK modems.
IET Circuits Devices Syst., 2017

CORDIC-based Hann windowed sliding DFT architecture for real-time spectrum analysis with bounded error-accumulation.
IET Circuits Devices Syst., 2017

Fraction phase based low energy frequency calibration: analysis and design.
IET Circuits Devices Syst., 2017

Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations.
J. Electron. Test., 2017

Algorithm/Architecture Co-design of Proportionate-type LMS Adaptive Filters for Sparse System Identification.
CoRR, 2017

Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs.
Proceedings of the 24th IEEE International Conference on High Performance Computing, 2017

2016
Choice of granularity for reliable circuit design using dynamic reconfiguration.
Microelectron. Reliab., 2016

Erratum to: A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation.
J. Real Time Image Process., 2016

A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation.
J. Real Time Image Process., 2016

High Performance VISI Design of Diamond Search Algorithm for Fast Motion Estimation.
J. Circuits Syst. Comput., 2016

Low-Delay Parallel Architecture for Fractal Image Compression.
Circuits Syst. Signal Process., 2016

Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Approximate conditional carry adder for error tolerant applications.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

High performance bit-sliced pipelined comparator tree for FPGAs.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015
Real-time fault-tolerance with hot-standby topology for conditional sum adder.
Microelectron. Reliab., 2015

High Performance VLSI Architecture for Three-Step Search Algorithm.
Circuits Syst. Signal Process., 2015

New triple-transistor based defect-tolerant systems for reliable digital architectures.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
CORDIC-Based VLSI Architecture for Implementing Kaiser-Bessel Window in Real Time Spectral Analysis.
J. Signal Process. Syst., 2014

VLSI design of fast fractal image encoder.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

An ultra low power MICS/ISM band transmitter in 0.18 μm CMOS.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

2013
Pipelined VLSI Architecture using CORDIC for Transform Domain Equalizer.
J. Signal Process. Syst., 2013

VLSI architecture for parallel radix-4 CORDIC.
Microprocess. Microsystems, 2013

2012
A Variable RF Carrier Modulation Scheme for Ultralow Power Wireless Body-Area Network.
IEEE Syst. J., 2012

Random Access Analog Memory (RA2M) for Video Signal Application.
Proceedings of the 25th International Conference on VLSI Design, 2012

Design of a Fault-Tolerant Conditional Sum Adder.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture.
Proceedings of the International Symposium on Electronic System Design, 2012

2011
VLSI architecture for low latency radix-4 CORDIC.
Comput. Electr. Eng., 2011

2010
CORDIC Architectures: A Survey.
VLSI Design, 2010

Architectural design and FPGA implementation of radix-4 CORDIC processor.
Microprocess. Microsystems, 2010

Design of DXT architecture using current switched integrator.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2008
High Throughput VLSI Architecture for Blackman Windowing in Real Time Spectral Analysis.
J. Comput., 2008

2006
Sampled analog architecture for 2-D DCT.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
A trigonometric formulation of the LMS algorithm for realization on pipelined CORDIC.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

Novel architecture for QAM modulator-demodulator and its generalization to multicarrier modulation.
Microprocess. Microsystems, 2005

Design Issues in Switched Capacitor Ladder Filters.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2004
Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Sampled analog architecture for DCT and DST.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Digital controlled analog architecture for DCT and DST using capacitor switching.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Analog sampled data architecture for discrete Hartley transform for prime N.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2001
A VLSI array architecture for realization of DFT, DHT, DCT and DST.
Signal Process., 2001

FPGA realization of a CORDIC based FFT processor for biomedical signal processing.
Microprocess. Microsystems, 2001

CORDIC realization of the transversal adaptive filter using a trigonometric LMS algorithm.
Proceedings of the IEEE International Conference on Acoustics, 2001

2000
Systolizing the adaptive decision feedback equalizer using a symbolic state space formulation.
Proceedings of the 10th European Signal Processing Conference, 2000

1992
An Array Architecture for Computing KLT Basis Vectors.
Proceedings of the Fifth International Conference on VLSI Design, 1992


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