Aysha S. Shanta

Orcid: 0000-0003-0811-0047

According to our database1, Aysha S. Shanta authored at least 10 papers between 2017 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2021
Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map.
CoRR, 2021

2020
A Chaos-Based Complex Micro-instruction Set for Mitigating Instruction Reverse Engineering.
J. Hardw. Syst. Secur., 2020

2019
Design of a Lightweight Reconfigurable PRNG Using Three Transistor Chaotic Map.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Memristor Crossbar PUF based Lightweight Hardware Security for IoT.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

Design for Eliminating Operation Specific Power Signatures from Digital Logic.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
Design of a Reconfigurable Chaos Gate with Enhanced Functionality Space in 65nm CMOS.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Carbon Nanospikes on Silicon Wafer for Amperometric Biosensing Applications.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

2017
A sub-μW CMOS temperature to frequency sensor for implantable devices.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Carbon nanospikes for biosensing applications.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017


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