Md Sakib Hasan

Orcid: 0000-0002-4792-6236

According to our database1, Md Sakib Hasan authored at least 34 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Biomembrane-Based Memcapacitive Reservoir Computing System for Energy-Efficient Temporal Data Processing.
Adv. Intell. Syst., December, 2023

Robust Chaos With Novel 4-Transistor Maps.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

Brain-Inspired Reservoir Computing Using Memristors with Tunable Dynamics and Short-Term Plasticity.
CoRR, 2023

Spike-based Neuromorphic Computing for Next-Generation Computer Vision.
CoRR, 2023

Energy-efficient memcapacitive physical reservoir computing system for temporal data processing.
CoRR, 2023

Compact Analog Chaotic Map Designs Using SOI Four-Gate Transistors.
IEEE Access, 2023

Split-Slope Chaotic Map Providing High Entropy Across Wide Range.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2022
A 2D Chaotic Oscillator for Analog IC.
IEEE Open J. Circuits Syst., 2022

Cascading CMOS-Based Chaotic Maps for Improved Performance and Its Application in Efficient RNG Design.
IEEE Access, 2022

Design, Analysis, and Application of Flipped Product Chaotic System.
IEEE Access, 2022

2021
Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Design of a Dynamic Parameter-Controlled Chaotic-PRNG in a 65nm CMOS process.
CoRR, 2021

Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map.
CoRR, 2021

Design of a Weighted Average Chaotic System for Robust Chaotic Operation.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Design and Application of a Novel 4-Transistor Chaotic Map with Robust Performance.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

Self-Parameterized Chaotic Map: A Hardware-efficient Scheme Providing Wide Chaotic Range.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

Design of a Low-Overhead Random Number Generator Using CMOS-based Cascaded Chaotic Maps.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
A Chaos-Based Complex Micro-instruction Set for Mitigating Instruction Reverse Engineering.
J. Hardw. Syst. Secur., 2020

A Secure Back-up and Restore for Resource-Constrained IoT based on Nanotechnology.
CoRR, 2020

2019
A Secure Integrity Checking System for Nanoelectronic Resistive RAM.
IEEE Trans. Very Large Scale Integr. Syst., 2019

DC modelling of SOI four-gate transistor (G<sup>4</sup>FET) for implementation in circuit simulator using multivariate regression polynomial.
IET Circuits Devices Syst., 2019

Modeling of Silicon Photomultiplier Based on Perimeter Gated Single Photon Avalanche Diode.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Design of a Lightweight Reconfigurable PRNG Using Three Transistor Chaotic Map.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Design Considerations for Insulator Metal Transition based Artificial Neurons.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Stochasticity in Neuromorphic Computing: Evaluating Randomness for Improved Performance.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

A Scan Register Based Access Scheme for Multilevel Non-Volatile Memristor Memory.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Memristor Crossbar PUF based Lightweight Hardware Security for IoT.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

On the Theoretical Analysis of Memristor based True Random Number Generator.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Design for Eliminating Operation Specific Power Signatures from Digital Logic.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
Modeling of SOI four-gate transistor (G<sup>4</sup>FET) using multidimensional spline interpolation method.
Microelectron. J., 2018

Design of a Reconfigurable Chaos Gate with Enhanced Functionality Space in 65nm CMOS.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Chaos computing for mitigating side channel attack.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

A Soft-Matter Biomolecular Memristor Synapse for Neuromorphic Systems.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017
Numerical modeling and implementation in circuit simulator of SOI four-gate transistor (G<sup>4</sup>FET) using multidimensional Lagrange and Bernstein polynomial.
Microelectron. J., 2017


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