Md. Badruddoja Majumder

Orcid: 0000-0003-4295-9853

According to our database1, Md. Badruddoja Majumder authored at least 17 papers between 2016 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map.
CoRR, 2021

2020
A Chaos-Based Complex Micro-instruction Set for Mitigating Instruction Reverse Engineering.
J. Hardw. Syst. Secur., 2020

A Secure Back-up and Restore for Resource-Constrained IoT based on Nanotechnology.
CoRR, 2020

2019
A Secure Integrity Checking System for Nanoelectronic Resistive RAM.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Design of a Lightweight Reconfigurable PRNG Using Three Transistor Chaotic Map.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Memristor Crossbar PUF based Lightweight Hardware Security for IoT.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

Design for Eliminating Operation Specific Power Signatures from Digital Logic.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
Design Considerations for Memristive Crossbar Physical Unclonable Functions.
ACM J. Emerg. Technol. Comput. Syst., 2018

Practical realisation of a return map immune Lorenz-based chaotic stream cipher in circuitry.
IET Comput. Digit. Tech., 2018

Nanoelectronic Security Designs for Resource-Constrained Internet of Things Devices: Finding Security Solutions with Nanoelectronic Hardwares.
IEEE Consumer Electron. Mag., 2018

Design of a Reconfigurable Chaos Gate with Enhanced Functionality Space in 65nm CMOS.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Chaos computing for mitigating side channel attack.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

2017
Exploiting Memristive Crossbar Memories as Dual-Use Security Primitives in IoT Devices.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
Techniques for Improved Reliability in Memristive Crossbar PUF Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A Designer's Rationale for Nanoelectronic Hardware Security Primitives.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Sneak path enabled authentication for memristive crossbar memories.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016


  Loading...