Garrett S. Rose
Orcid: 0000-0003-3070-4087Affiliations:
- University of Tennessee, Knoxville, USA
According to our database1,
Garrett S. Rose
authored at least 140 papers
between 2004 and 2024.
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Bibliography
2024
SpiCS-Net: Circuit Switched Network on Chip for Area-Efficient Spiking Recurrent Neural Networks.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023
Reimagining Sense Amplifiers: Harnessing Phase Transition Materials for Current and Voltage Sensing.
CoRR, 2023
Enhanced Read Resolution in Reconfigurable Memristive Synapses for Spiking Neural Networks.
CoRR, 2023
A Single Chip SPAD Based Vision Sensing System With Integrated Memristive Spiking Neuromorphic Processing.
IEEE Access, 2023
Energy Efficient and High-Performance Synaptic Operating Point Evaluation for SNN Applications.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Algorithm and Application Impacts of Programmable Plasticity in Spiking Neuromorphic Hardware.
Proceedings of the 2023 International Conference on Neuromorphic Systems, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
RFAM: RESET-Failure-Aware-Model for HfO2-based Memristor to Enhance the Reliability of Neuromorphic Design.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
A Mixed-Signal Short-Term Plasticity Implementation for a Current-Controlled Memristive Synapse.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023
2022
Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things.
ACM J. Emerg. Technol. Comput. Syst., 2022
Unsupervised Digit Recognition Using Cosine Similarity In A Neuromemristive Competitive Learning System.
ACM J. Emerg. Technol. Comput. Syst., 2022
A Generalized Workflow for Creating Machine Learning-Powered Compact Models for Multi-State Devices.
IEEE Access, 2022
A Framework to Enable Top-Down Co-Design of Neuromorphic Systems for Real-World Applications.
Proceedings of the NICE 2022: Neuro-Inspired Computational Elements Conference, 2022
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Programmable Refractory Period Implementations in a Mixed-Signal Integrate-And-Fire Neuron.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Benchmark Comparisons of Spike-based Reconfigurable Neuroprocessor Architectures for Control Applications.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
2021
Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Neuromorph. Comput. Eng., 2021
Design of a Robust Memristive Spiking Neuromorphic System with Unsupervised Learning in Hardware.
ACM J. Emerg. Technol. Comput. Syst., 2021
Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map.
CoRR, 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Scaling Constraints for Memristor-based Programmable Interconnect in Reconfigurable Computing Arrays.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
2020
A Chaos-Based Complex Micro-instruction Set for Mitigating Instruction Reverse Engineering.
J. Hardw. Syst. Secur., 2020
Device-aware Circuit Design for Robust Memristive Neuromorphic Systems with STDP-based Learning.
ACM J. Emerg. Technol. Comput. Syst., 2020
Towards Synaptic Behavior of Nanoscale ReRAM Devices for Neuromorphic Computing Applications.
ACM J. Emerg. Technol. Comput. Syst., 2020
CoRR, 2020
Single Photon Avalanche Diode based Vision Sensor with On-Chip Memristive Spiking Neuromorphic Processing.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Circuit Techniques for Efficient Implementation of Memristor Based Reservoir Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Scaled-up Neuromorphic Array Communications Controller (SNACC) for Large-scale Neural Networks.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
A Multi-Driver Write Scheme for Reliable and Energy Efficient 1S1R ReRAM Crossbar Arrays.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Fabrication and Performance of Hybrid ReRAM-CMOS Circuit Elements for Dynamic Neural Networks.
Proceedings of the International Conference on Neuromorphic Systems, 2019
Stochasticity in Neuromorphic Computing: Evaluating Randomness for Improved Performance.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the IEEE International Conference on Consumer Electronics, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
2018
ACM J. Emerg. Technol. Comput. Syst., 2018
A Study of Complex Deep Learning Networks on High-Performance, Neuromorphic, and Quantum Computers.
ACM J. Emerg. Technol. Comput. Syst., 2018
Practical realisation of a return map immune Lorenz-based chaotic stream cipher in circuitry.
IET Comput. Digit. Tech., 2018
Memristive Mixed-Signal Neuromorphic Systems: Energy-Efficient Learning at the Circuit-Level.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Nanoelectronic Security Designs for Resource-Constrained Internet of Things Devices: Finding Security Solutions with Nanoelectronic Hardwares.
IEEE Consumer Electron. Mag., 2018
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
Design of a Reconfigurable Chaos Gate with Enhanced Functionality Space in 65nm CMOS.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
A Mixed-Mode Neuron with On-chip Tunability for Generic Use in Memristive Neuromorphic Systems.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
A bi-memristor synapse with spike-timing-dependent plasticity for on-chip learning in memristive neuromorphic systems.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
Energy and Area Efficiency in Neuromorphic Computing for Resource Constrained Devices.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
Proceedings of the Neuromorphic Computing Symposium, 2017
Proceedings of the Neuromorphic Computing Symposium, 2017
Proceedings of the 4th ACM International Conference on Nanoscale Computing and Communication, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Exploiting Memristive Crossbar Memories as Dual-Use Security Primitives in IoT Devices.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
A practical hafnium-oxide memristor model suitable for circuit design and simulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A Unified Hardware/Software Co-Design Framework for Neuromorphic Computing Devices and Applications.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017
Circuit Techniques for Online Learning of Memristive Synapses in CMOS-Memristor Neuromorphic Systems.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
2015
Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors.
IEEE Trans. Computers, 2015
Proc. IEEE, 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
Hardware-Based Computational Intelligence for Size, Weight, and Power Constrained Environments.
Proceedings of the Network Science and Cybersecurity, 2014
Proceedings of the Network Science and Cybersecurity, 2014
Proceedings of the Network Science and Cybersecurity, 2014
IEEE Trans. Neural Networks Learn. Syst., 2014
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
2013
IEEE Trans. Computers, 2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the 2013 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Proc. IEEE, 2012
ACM J. Emerg. Technol. Comput. Syst., 2012
Exploiting memristive device behavior for emerging digital logic and memory applications.
Proceedings of the IEEE 25th International SOC Conference, 2012
RRAM-based adaptive neural logic block for implementing non-linearly separable functions in a single layer.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
ACM J. Emerg. Technol. Comput. Syst., 2011
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A low-power memristive neuromorphic circuit utilizing a global/local training mechanism.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011
2010
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
2009
IET Comput. Digit. Tech., 2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
ACM J. Emerg. Technol. Comput. Syst., 2007
On-chip characterization of molecular electronic devices using CMOS: the design and simulation of a hybrid circuit based on experimental molecular electronic device results.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Design approaches for hybrid CMOS/molecular memory based on experimental device data.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004