B. P. Harish

According to our database, B. P. Harish authored at least 11 papers between 2007 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

A Novel Feasibility Test for Energy Minimization of Real-Time Mixed Task Sets for DVS-Enabled Uniprocessor System.

H. T. Manohara, B. P. Harish

J. Circuits Syst. Comput., 2022

2020

Process-induced variability modeling of subthreshold leakage power considering device stacking.

Anala M. Reddy, B. P. Harish

Int. J. Circuit Theory Appl., 2020

Artificial Neural Network Model for Design Optimization of 2-stage Op-amp.

Harsha M. V., B. P. Harish

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

2019

Dynamic Supply Voltage Level Generation for Minimum Energy Real Time Tasks using Geometric Programming.

H. T. Manohara, B. P. Harish

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Process Variation-Aware Analytical Modeling of Subthreshold Leakage Power.

Anala M., B. P. Harish

Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

2018

An Integrated MaxFit Genetic Algorithm-SPICE Framework for 2-Stage Op-Amp Design Automation.

Harsha M. V., B. P. Harish

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Analytical Modeling of Process Variability in Subthreshold Regime for Ultra Low Power Applications.

Anala M., B. P. Harish

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2009

Bridging Technology-CAD and Design-CAD for Variability Aware Nano-CMOS Circuits.

B. P. Harish, Navakanta Bhat, Mahesh B. Patil

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Hybrid-CV Modeling for Estimating the Variability in Dynamic Power.

B. P. Harish, Navakanta Bhat, Mahesh B. Patil

J. Low Power Electron., 2008

2007

On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology.

B. P. Harish, Navakanta Bhat, Mahesh B. Patil

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs.

B. P. Harish, Navakanta Bhat, Mahesh B. Patil

Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007