Navakanta Bhat

According to our database, Navakanta Bhat authored at least 33 papers between 2002 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2018

Optoelectronics based on Vertical Transport in Multi-layer MoS2.

Shubhadeep Bhattacharjee, Pranandita Biswas, Swan Solanke, Rangarajan Muralidharan, Digbijoy Nath, Navakanta Bhat

Proceedings of the 76th Device Research Conference, 2018

2017

ESD Behavior of AlGaN/GaN HEMT on Si: Physical Insights, Design Aspects, Cumulative Degradation and Failure Analysis.

Bhawani Shankar, Ankit Soni, Manikant Singh, Rohith Soman, K. N. Bhat, Srinivasan Raghavan, Navakanta Bhat, Mayank Shrivastava

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Using dielectric droplets to improve sensitivity of capacitive sensors suitable for tactile sensing.

Saloni Chaurasia, Prosenjit Sen, Navakanta Bhat

Proceedings of the 12th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2017

2016

Impact of carrier quantum confinement on the short channel effects of double-gate silicon-on-insulator FINFETs.

AdityaSankar Medury, K. N. Bhat, Navakanta Bhat

Microelectron. J., 2016

Smart handheld platform for electrochemical bio sensors.

Suraj Hebbar, Vinay Kumar, M. S. Bhat, Navakanta Bhat

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2014

Improved Design Methodology for the Development of Electrically Actuated MEMS Structures.

A. V. S. S. Prasad, K. P. Venkatesh, Rudra Pratap, Navakanta Bhat

Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

High-performance stacked TiO2-ZrO2 and Si-doped ZrO2 metal-insulator-metal capacitors.

Revathy Padmanabhan, Navakanta Bhat, Yuichiro Morozumi, S. Mohan, Sanjeev Kaushal

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2012

A CMOS Gas Sensor Array Platform With Fourier Transform Based Impedance Spectroscopy.

Pramod Murali, Ranjit K., Navakanta Bhat, Gaurab Banerjee, Bharadwaj Amrutur, K. N. Bhat, Praveen C. Ramamurthy

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

CMOS Gas Sensor Array Platform with Fourier Transform Based Impedance Spectroscopy.

Pramod Murali, Navakanta Bhat, Gaurab Banerjee, Bharadwaj Amrutur, K. N. Bhat, Praveen C. Ramamurthy

Proceedings of the 25th International Conference on VLSI Design, 2012

2011

Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique.

Rakesh Gnana David Jeyasingh, Navakanta Bhat, Bharadwaj S. Amrutur

IEEE Trans. Very Large Scale Integr. Syst., 2011

Power Scalable Digital Baseband Architecture for IEEE 802.15.4.

Satyam Dwivedi, Bharadwaj Amrutur, Navakanta Bhat

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Detection of Glycated Hemoglobin using 3-Aminophenylboronic Acid Modified Graphene Oxide.

Siva Rama Krishna V., Bharadwaj Amrutur, Navakanta Bhat, Chakra Pani K., Sampath Srinivasan

Proceedings of the BIODEVICES 2011, 2011

2009

Performance Analysis of Subthreshold Cascode Current Mirror in 130 nm CMOS Technology.

Balaji Jayaraman, Navakanta Bhat

J. Low Power Electron., 2009

Bridging Technology-CAD and Design-CAD for Variability Aware Nano-CMOS Circuits.

B. P. Harish, Navakanta Bhat, Mahesh B. Patil

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Optimisation of Gate-Drain/Source Overlap in 90 nm NMOSFETs for Low Noise Amplifier Performance.

R. Srinivasan, Navakanta Bhat

J. Low Power Electron., 2008

Hybrid-CV Modeling for Estimating the Variability in Dynamic Power.

B. P. Harish, Navakanta Bhat, Mahesh B. Patil

J. Low Power Electron., 2008

GyroCompiler: A Soft IP Model Synthesis and Analysis Framework for Design of MEMS Based Gyroscopes.

Sukumar Jairam, Navakanta Bhat

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Optimal power and noise allocation for analog and digital sections of a low power radio receiver.

Kannan Aryaperumal Sankaragomathi, Manodipan Sahoo, Satyam Dwivedi, Bharadwaj S. Amrutur, Navakanta Bhat

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

A low power, process invariant keeper for high speed dynamic logic circuits.

Rakesh Gnana David Jeyasingh, Navakanta Bhat

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Verification of a MEMS based adaptive cruise control system using simulation and semi-formal approaches.

Sukumar Jairam, Kusum Lata, Subir K. Roy, Navakanta Bhat

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007

On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology.

B. P. Harish, Navakanta Bhat, Mahesh B. Patil

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Circuit prospects of DGFET: Variable gain differential amplifier an a schmitt trigger with adjustable hysteresis.

Srimoyee Sen, Urmimala Roy, Chaitanya Kshirsagar, Navakanta Bhat, Chandan Kumar Sarkar

Proceedings of the IFIP VLSI-SoC 2007, 2007

High Precision 16-bit Readout Gas Sensor Interface in 0.13µm CMOS.

Balaji Jayaraman, Navakanta Bhat

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs.

B. P. Harish, Navakanta Bhat, Mahesh B. Patil

Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

2005

Asymmetric cross-coupled differential pair configuration to realize neuron activation function and its derivative.

Amit K. Gupta, Navakanta Bhat

IEEE Trans. Circuits Syst. II Express Briefs, 2005

Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications.

R. Srinivasan, Navakanta Bhat

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2004

Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment.

H. C. Srinivasaiah, Navakanta Bhat

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Quasi Static Model for a Simply Supported Beam in a Circuit Simulation Framework.

Sukumar Jairam, C. Venkatesh, Navakanta Bhat, Shyam Singh, Rudra Pratap

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003

Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations.

H. C. Srinivasaiah, Navakanta Bhat

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Torsional Mems Varactor With Low Actuation Voltage.

C. Venkatesh, Shashidhar Pati, Navakanta Bhat

Int. J. Comput. Eng. Sci., 2003

Voltage Controlled Oscillator Using Tunable Mems Resonator.

Shashidhar Pati, C. Venkatesh, Navakanta Bhat, Rudra Pratap

Int. J. Comput. Eng. Sci., 2003

Effect of Scaling on the Non-quasi-static Behaviour of the MOSFET for RF IC's.

R. Srinivasan, Navakanta Bhat

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2002

Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay.

H. C. Srinivasaiah, Navakanta Bhat

Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002