Navakanta Bhat

According to our database1, Navakanta Bhat authored at least 33 papers between 2002 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Optoelectronics based on Vertical Transport in Multi-layer MoS2.
Proceedings of the 76th Device Research Conference, 2018

2017
ESD Behavior of AlGaN/GaN HEMT on Si: Physical Insights, Design Aspects, Cumulative Degradation and Failure Analysis.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Using dielectric droplets to improve sensitivity of capacitive sensors suitable for tactile sensing.
Proceedings of the 12th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2017

2016
Impact of carrier quantum confinement on the short channel effects of double-gate silicon-on-insulator FINFETs.
Microelectron. J., 2016

Smart handheld platform for electrochemical bio sensors.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2014
Improved Design Methodology for the Development of Electrically Actuated MEMS Structures.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

High-performance stacked TiO2-ZrO2 and Si-doped ZrO2 metal-insulator-metal capacitors.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2012
A CMOS Gas Sensor Array Platform With Fourier Transform Based Impedance Spectroscopy.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

CMOS Gas Sensor Array Platform with Fourier Transform Based Impedance Spectroscopy.
Proceedings of the 25th International Conference on VLSI Design, 2012

2011
Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Power Scalable Digital Baseband Architecture for IEEE 802.15.4.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Detection of Glycated Hemoglobin using 3-Aminophenylboronic Acid Modified Graphene Oxide.
Proceedings of the BIODEVICES 2011, 2011

2009
Performance Analysis of Subthreshold Cascode Current Mirror in 130 nm CMOS Technology.
J. Low Power Electron., 2009

Bridging Technology-CAD and Design-CAD for Variability Aware Nano-CMOS Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Optimisation of Gate-Drain/Source Overlap in 90 nm NMOSFETs for Low Noise Amplifier Performance.
J. Low Power Electron., 2008

Hybrid-CV Modeling for Estimating the Variability in Dynamic Power.
J. Low Power Electron., 2008

GyroCompiler: A Soft IP Model Synthesis and Analysis Framework for Design of MEMS Based Gyroscopes.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Optimal power and noise allocation for analog and digital sections of a low power radio receiver.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

A low power, process invariant keeper for high speed dynamic logic circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Verification of a MEMS based adaptive cruise control system using simulation and semi-formal approaches.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Circuit prospects of DGFET: Variable gain differential amplifier an a schmitt trigger with adjustable hysteresis.
Proceedings of the IFIP VLSI-SoC 2007, 2007

High Precision 16-bit Readout Gas Sensor Interface in 0.13µm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs.
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

2005
Asymmetric cross-coupled differential pair configuration to realize neuron activation function and its derivative.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2004
Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Quasi Static Model for a Simply Supported Beam in a Circuit Simulation Framework.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003
Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Torsional Mems Varactor With Low Actuation Voltage.
Int. J. Comput. Eng. Sci., 2003

Voltage Controlled Oscillator Using Tunable Mems Resonator.
Int. J. Comput. Eng. Sci., 2003

Effect of Scaling on the Non-quasi-static Behaviour of the MOSFET for RF IC's.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2002
Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002


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