Mahesh B. Patil

According to our database, Mahesh B. Patil authored at least 29 papers between 1998 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Circuit simulation using explicit methods: singular matrix issues.

Mahesh B. Patil

CoRR, 2023

Circuit simulation using explicit methods.

Mahesh B. Patil, V. V. S. Pavan Kumar Hari

CoRR, 2023

2022

An open-source simulation package for power electronics education.

Mahesh B. Patil, V. V. S. Pavan Kumar Hari, Ruchita D. Korgaonkar, Kumar Appaiah

CoRR, 2022

2021

GSEIM: A General-purpose Simulator with Explicit and Implicit Methods.

Mahesh B. Patil, Ruchita D. Korgaonkar, Kumar Appaiah

CoRR, 2021

2020

A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping.

Sitansusekhar Roymohapatra, Ganesh R. Gore, Akanksha Yadav, Mahesh B. Patil, Krishnan S. Rengarajan, Subramanian S. Iyer, Maryam Shojaei Baghini

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Multi-Objective Optimisation of Damper Placement for Improved Seismic Response in Dynamically Similar Adjacent Buildings.

Mahesh B. Patil, Ramakrishna U., Mohan S. C

CoRR, 2020

2019

Water Distribution System Design Using Multi-Objective Genetic Algorithm with External Archive and Local Search.

Mahesh B. Patil, M. Naveen Naidu, A. Vasan, Murari R. R. Varma

CoRR, 2019

Water Distribution System Design Using Multi-Objective Particle Swarm Optimisation.

Mahesh B. Patil, M. Naveen Naidu, A. Vasan, Murari R. R. Varma

CoRR, 2019

2018

Using External Archive for Improved Performance in Multi-Objective Optimization.

Mahesh B. Patil

CoRR, 2018

2017

Enhanced Look-Up Table Approach for Modeling of Floating Body SOI MOSFET.

Sitansusekhar Roymohapatra, Ganesh R. Gore, Akanksha Yadav, Mahesh B. Patil, Krishnan S. Rengrajan, Maryam Shojaei Baghini

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2013

An approach to complement electronics courses using virtual environment.

Jinu Jayachandran, Nina Joseph, Maheshwar Mangat, Vinay Verma, N. P. Narendra, Aniruddha Shastri, Devendra Patil, Madhumita Date, Joseph John, Mahesh B. Patil

Proceedings of the IEEE Global Engineering Education Conference, 2013

2011

A novel architecture for improving slew rate in FinFET-based op-amps and OTAs.

Rajesh Amratlal Thakker, Mayank Srivastava, Ketankumar H. Tailor, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao, Mahesh B. Patil

Microelectron. J., 2011

2010

A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance.

Rajesh Amratlal Thakker, Chaitanya Sathe, Maryam Shojaei Baghini, Mahesh B. Patil

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework.

Angada B. Sachid, Rajesh Amratlal Thakker, Chaitanya Sathe, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao, Mahesh B. Patil

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009

A Novel Table-Based Approach for Design of FinFET Circuits.

Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Automatic Design of Low-Power Low-Voltage Analog Circuits Using Particle Swarm Optimization with Re-Initialization.

Rajesh Amratlal Thakker, Maryam Shojaei Baghini, Mahesh B. Patil

J. Low Power Electron., 2009

Parameter extraction for PSP MOSFET model using hierarchical particle swarm optimization.

Rajesh Amratlal Thakker, Mahesh B. Patil, K. G. Anil

Eng. Appl. Artif. Intell., 2009

Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization.

Rajesh Amratlal Thakker, Maryam Shojaei Baghini, Mahesh B. Patil

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Bridging Technology-CAD and Design-CAD for Variability Aware Nano-CMOS Circuits.

B. P. Harish, Navakanta Bhat, Mahesh B. Patil

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Automated design and optimization of circuits in emerging technologies.

Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Hybrid-CV Modeling for Estimating the Variability in Dynamic Power.

B. P. Harish, Navakanta Bhat, Mahesh B. Patil

J. Low Power Electron., 2008

2007

On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology.

B. P. Harish, Navakanta Bhat, Mahesh B. Patil

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs.

B. P. Harish, Navakanta Bhat, Mahesh B. Patil

Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

2006

Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits.

Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2003

Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits.

D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2002

A new public-domain simulator for power electronic circuits.

Mahesh B. Patil, Shyama P. Das, Avinash Joshi, Mukul Chandorkar

IEEE Trans. Educ., 2002

1999

Extension of the VR discretization scheme for velocity saturation.

Mahesh B. Patil

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998

Numerical Evaluation of Iterative Schemes for Drift-diffusion Simulation.

Mahesh B. Patil, Umberto Ravaioli, Thomas Kerkhoven

VLSI Design, 1998

New discretization scheme for two-dimensional semiconductor device simulation on triangular grid.

Mahesh B. Patil

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998