Babak Sadiye

According to our database, Babak Sadiye authored at least 5 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.

Babak Sadiye, Mohammed Iftekhar, Wolfgang Müller, Johann-Christoph Scheytt

IEEE Trans. Very Large Scale Integr. Syst., February, 2026

2025

Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits.

Tobias Schwabe, Christian Kress, Babak Sadiye, Stephan Kruse, Johann-Christoph Scheytt

IEEE Access, 2025

2024

A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing.

Paul Palomero Bernardo, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar, Babak Sadiye, Wolfgang Müller, Andreas Koch, Eyck Jentzsch, Axel Sauer, Ingo Feldner, Wolfgang Ecker

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.

Lars Luchterhandt, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Mueller, Babak Sadiye

Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2023

A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology.

Mohammed Iftekhar, Harshan Gowda, Pascal Kneuper, Babak Sadiye, Wolfgang Müller, Johann-Christoph Scheytt

Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2023