Rainer Dömer

According to our database1, Rainer Dömer authored at least 79 papers between 1994 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Analyzing Variable Entanglement for Parallel Simulation of SystemC TLM-2.0 Models.
ACM Trans. Embedded Comput. Syst., 2019

2018
SystemC Coding Guideline for Faster Out-of-order Parallel Discrete Event Simulation.
Proceedings of the 2018 Forum on Specification & Design Languages, 2018

Port call path sensitive conflict analysis for instance-aware parallel SystemC simulation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
SCE: System-on-Chip Environment.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Introduction to Hardware/Software Codesign.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Parallel Simulation.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Thread- and data-level parallel simulation in SystemC, a Bitcoin miner case study.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

Exploiting Thread and Data Level Parallelism for Ultimate Parallel SystemC Simulation.
Proceedings of the 54th Annual Design Automation Conference, 2017

Hybrid analysis of SystemC models for fast and accurate parallel simulation.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Seven Obstacles in the Way of Standard-Compliant Parallel SystemC Simulation.
Embedded Systems Letters, 2016

Automatic Generation of Thread Communication Graphs from SystemC Source Code.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

A segment-aware multi-core scheduler for system C PDES.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

2015
May-happen-in-parallel analysis of ESL models using UPPAAL model checking.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Optimizing thread-to-core mapping on manycore platforms with distributed Tag Directories.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Communication protocol analysis of transaction-level models using Satisfiability Modulo Theories.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

A program state machine based virtual processing model in SystemC.
SIGBED Review, 2014

Automated estimation of power consumption for rapid system level design.
Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014

Powermonitor: a versatile API for automated power-aware ESL design.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

May-happen-in-parallel analysis based on segment graphs for safe ESL models.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Advances in Parallel Discrete Event Simulation for Electronic System-Level Design.
IEEE Design & Test, 2013

Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis.
Proceedings of the International Workshop on Software and Compilers for Embedded Systems, 2013

Formal Deadlock Analysis of SpecC Models Using Satisfiability Modulo Theories.
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013

TECSCE: HW/SW Codesign Framework for Data Parallelism Based on Software Component.
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013

Optimized out-of-order parallel discrete event simulation using predictions.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Computer-Aided Recoding to Create Structured and Analyzable System Models.
ACM Trans. Embedded Comput. Syst., 2012

Eliminating race conditions in system-level models by using parallel simulation infrastructure.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Out-of-order parallel simulation for ESL design.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Parallel discrete event simulation of Transaction Level Models.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

An optimizing compiler for out-of-order parallel ESL simulation exploiting instance isolation.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Multicore Simulation of Transaction-Level Models Using the SoC Environment.
IEEE Design & Test of Computers, 2011

Multi-core parallel simulation of System-level Description Languages.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Fast and accurate processor models for efficient MPSoC design.
ACM Trans. Design Autom. Electr. Syst., 2010

ESL design and multi-core validation using the System-on-Chip Environment.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

Panel Session - Who Is Closing the embedded software design gap?
Proceedings of the Design, Automation and Test in Europe, 2010

System-level development of embedded software.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Computer-aided recoding for multi-core systems.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

A fast heuristic scheduling algorithm for periodic ConcurrenC models.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
A Configurable TLM of Wireless Sensor Networks for Fast Exploration of System Communication Performance.
Proceedings of the Analysis, 2009

Efficient Modeling of Embedded Systems Using Computer-Aided Recoding.
Proceedings of the Analysis, 2009

ConcurrenC: A New Approach towards Effective Abstraction of C-Based SLDLs.
Proceedings of the Analysis, 2009

Programming MPSoC platforms: Road works ahead!
Proceedings of the Design, Automation and Test in Europe, 2009

Introduction to hardware-dependent software design hardware-dependent software for multi- and many-core embedded systems.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors.
IEEE Trans. VLSI Syst., 2008

Quantitative analysis of the speed/accuracy trade-off in transaction level modeling.
ACM Trans. Embedded Comput. Syst., 2008

Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design.
EURASIP J. Emb. Sys., 2008

Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling.
Proceedings of the Design, Automation and Test in Europe, 2008

Automatic generation of hardware dependent software for MPSoCs from abstract system specifications.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Automatic re-coding of reference code into structured and analyzable SoC models.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Result-Oriented Modeling - A Novel Technique for Fast and Accurate TLM.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Automatic Layer-Based Generation of System-On-Chip Bus Communication Models.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

An Interactive Design Environment for C-based High-Level Synthesis.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Embedded Software Development in a System-Level Design Flow.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

An Interactive Model Re-Coder for Efficient SoC Specification.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification.
Proceedings of the 44th Design Automation Conference, 2007

Pointer re-coding for creating definitive MPSoC models.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Abstract, Multifaceted Modeling of Embedded Processors for System Level Design.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Creating Explicit Communication in SoC Models Using Interactive Re-Coding.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Fast and accurate transaction level models using result oriented modeling.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A Flexible, Syntax Independent Representation (SIR) for System Level Design Models.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Quantitative analysis of transaction level models for the AMBA bus.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Automatic generation of transaction level models for rapid design space exploration.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Accurate yet fast modeling of real-time communication.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005
Software and Driver Synthesis from Transaction Level Models.
Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005

Automatic Generation of Communication Architectures.
Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005

Abstract Communication Modeling.
Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005

Automatic network generation for system-on-chip communication design.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

System-level communication modeling for network-on-chip synthesis.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Embedded software generation from system level design languages.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2002
The Formal Execution Semantics of SpecC.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

2001
System Design - A Practical Guide with SpecC.
Springer, ISBN: 978-0-7923-7387-2, 2001

2000
System-level modeling and design with the SpecC language.
PhD thesis, 2000

Reuse and protection of intellectual property in the SpecC system.
Proceedings of ASP-DAC 2000, 2000

1998
Specification and Design of Embedded Systems.
it+ti - Informationstechnik und Technische Informatik, 1998

IP-Centric Methodology and Specification Language.
Proceedings of the Distributed and Parallel Embedded Systems, 1998

1997
Built-in chaining: introducing complex components into architectural synthesis.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
A Technique for Avoiding Isomorphic Netlists in Architectural Synthesis.
Proceedings of the 1996 European Design and Test Conference, 1996

1994
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming.
Proceedings of the Proceedings EURO-DAC'94, 1994


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