Wolfgang Ecker

According to our database1, Wolfgang Ecker authored at least 93 papers between 1992 and 2019.

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Bibliography

2019
Using Machine Learning for predicting area and Firmware metrics of hardware designs from abstract specifications.
Microprocessors and Microsystems - Embedded Hardware Design, 2019

Towards a Python-Based One Language Ecosystem for Embedded Systems Automation.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

How to Keep 4-Eyes Principle in a Design and Property Generation Flow.
Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019

Formal Verification Methodology in an Industrial Setup.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Embedded Systems' Automation following OMG's Model Driven Architecture Vision.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Increasing Soft Error Resilience by Software Transformation.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Meta-model Based Automation of Properties for Pre-Silicon Verification.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Quality Assessment of Generated Hardware Designs Using Statistical Analysis and Machine Learning.
Proceedings of the 8th International Workshop on Combinations of Intelligent Methods and Applications co-located with 30th International Conference on Artificial Intelligence Tools (ICTAI 2018), 2018

Analog fault simulation automation at schematic level with random sampling techniques.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017
Metamodeling and Code Generation in the Hardware/Software Interface Domain.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping.
Proceedings of the International Symposium on Rapid System Prototyping, 2017

Python based framework for HDSLs with an underlying formal semantics: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

On generation of properties from specification.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

2016
Speeding up safety verification by fault abstraction and simulation to transaction level.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Digital Hardware Design Based on Metamodels and Model Transformations.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Earth Mover's Distance as a Comparison Metric for Analog Behavior.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Automatically comparing analog behavior using Earth Mover's Distance.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Efficient handling of the fault space in functional safety analysis utilizing formal methods.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Gate-Level-Accurate Fault-Effect Analysis at Virtual-Prototype Speed.
Proceedings of the Computer Safety, Reliability, and Security, 2016

Where formal verification can help in functional safety analysis.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Design centric modeling of digital hardware.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

Fault-effect analysis on system-level hardware modeling using virtual prototypes.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

Transformation of Failure Propagation Models into Fault Trees for Safety Evaluation Purposes.
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2016

Efficient Checkpointing-Based Safety-Verification Flow Using Compiled-Code Simulation.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
The metamodeling approach to system level synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014


Metasynthesis for Designing Automotive SoCs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A transaction-oriented UVM-based library for verification of analog behavior.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
The semantic of the power intent format UPF: Consistent power modeling from system level to implementation.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Comparison of analog transactions using statistics.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Transaction-Level Modeling and Refinement Using State Charts.
Proceedings of the Computer Aided Systems Theory - EUROCAST 2013, 2013

2012
Single-source hardware modeling of different abstraction levels with State Charts.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

The system verification methodology for advanced TLM verification.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Testbenches for advanced TLM verification.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

SystemC as completing pillar in industrial OVM based verification environments.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Analog transaction level modeling.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

2010
Fast and accurate UML State Chart modeling using TLM+ control flow abstraction.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

Model reduction techniques for the formal verification of hardware dependent software.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

TLM+ modeling of embedded HW/SW systems.
Proceedings of the Design, Automation and Test in Europe, 2010

Panel Session - Who Is Closing the embedded software design gap?
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Using a dataflow abstracted virtual prototype for HdS-design.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Industrial IP Integration Flows based on IP-XACT Standards.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Requirements and Concepts for Transaction Level Assertion Refinement.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Interactive presentation: Implementation of a transaction level assertion framework in SystemC.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Execution semantics and formalisms for multi-abstraction TLM assertions.
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

Requirements and Concepts for Transaction Level Assertions.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Specification Language for Transaction Level Assertions.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

IP Library For Temporal SystemC Assertions.
Proceedings of the Forum on specification and Design Languages, 2006

Case Study on Transaction Level Modeling.
Proceedings of the Forum on specification and Design Languages, 2006

2005
Evolution of Paradigm Shifts in the Automated Design Process of Digital Circuits.
Proceedings of the INFORMATIK 2005, 2005

2004
A Layered Adaptive Verification Platform for Simulation, Test, and Emulation.
IEEE Design & Test of Computers, 2004

Ein orthogonales Schema für die Klassifikation der Modellierungsabstraktion von digitalen Systemen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

How to Bridge the Gap Between Simulationand Test.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Memory Models for the Formal Verification of Assembler Code Using Bounded Model Checking.
Proceedings of the 7th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2004), 2004

The Formal Simulation Semantics of SystemVerilog.
Proceedings of the Forum on specification and Design Languages, 2004

Extending the RASSP model for Verification.
Proceedings of the Forum on specification and Design Languages, 2004

SystemVerilog: Interface Based Design.
Proceedings of the Forum on specification and Design Languages, 2004

2003
An Enhanced Environment for Multi-Level Simulation.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

Incremental Design: A VHDL based Case Study.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

An Approach for Mixed Coarse-Granular and Fine-Granular Re-Configurable Architectures.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Platform-Based Testbench Generation.
Proceedings of the 2003 Design, 2003

Re-use-centric architecture for a fully accelerated testbench environment.
Proceedings of the 40th Design Automation Conference, 2003

2002
Verifikation und Wiederverwendung (Verification and Re-Use).
it+ti - Informationstechnik und Technische Informatik, 2002

2001
Hardware-basierter Hardware-Entwurf.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001

2000
Eine flexible Simulationsumgebung für System-On-Chip Design (A Flexible Simulation Environment for System-On-Chip Design).
it+ti - Informationstechnik und Technische Informatik, 2000

VXML: VHDL Hardware Design Representation in XML.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

Graphische Spezifikation und Analyse funktionaler Testabläufe mit MSCs der UML.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

An Open VHDL-AMS Simulation Framework.
Proceedings of the 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, 2000

1999
A scalable multithreaded compiler front-end.
Proceedings of the Parallel Computing: Fundamentals & Applications, 1999

A Method for Accelerating Test Environments.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998
Reuse-Potentiale im Hardware-Entwurf.
it+ti - Informationstechnik und Technische Informatik, 1998

1997
The Shall-Prototype-Test Development model.
Proceedings of the 1997 Workshop on Engineering of Computer-Based Systems (ECBS '97), 1997

Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach.
Proceedings of the 34st Conference on Design Automation, 1997

1996
VHDL synthesis description portability: The need for Level synthesis subsets.
Journal of Systems Architecture, 1996

Verification methods for VHDL RTL-subroutines.
Journal of Systems Architecture, 1996

Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionality.
Proceedings of the conference on European design automation, 1996

1995
VHDL-based communication and synchronization synthesis.
Proceedings of the Proceedings EURO-DAC'95, 1995

A classification of design steps and their verification.
Proceedings of the Proceedings EURO-DAC'95, 1995

Semi-dynamic scheduling of synchronization-mechanisms.
Proceedings of the Proceedings EURO-DAC'95, 1995

1994
Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations.
Proceedings of the Proceedings EURO-DAC'94, 1994

1993
State look ahead technique for cycle optimization of interacting finite state Moore machines.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Using VHDL for HW/SW co-specification.
Proceedings of the European Design Automation Conference 1993, 1993

System-Level Specification and Design Using VHDL: A Case Study.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993

1992
Subtype concept of VHDL for synthesis constraints.
Proceedings of the conference on European design automation, 1992

The design cube: a new model for VHDL designflow representation.
Proceedings of the conference on European design automation, 1992

Towards a common RT-level subset of VHDL.
Proceedings of the conference on European design automation, 1992


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