Wolfgang Ecker
Orcid: 0000-0002-9362-8096Affiliations:
- Infineon Technologies AG, Munich, Germany
- Technical University of Munich, Germany
According to our database1,
Wolfgang Ecker
authored at least 136 papers
between 1992 and 2023.
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Bibliography
2023
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications.
ACM Trans. Design Autom. Electr. Syst., March, 2023
IEEE Des. Test, February, 2023
FPGA-implementation techniques to efficiently test application readiness of mixed-signal products.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Effective Processor Model Generation from Instruction Set Simulator to Hardware Design.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
Using Graph Neural Networks for Timing Estimations of RTL Intermediate Representations.
Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023
Modelling Peripheral Designs using FSM-like Notation for Complete Property Set Generation.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Generator IP-reuse and Automated Infrastructure Generation for Model-based Full-Chip Generation.
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2023
Parallel Golomb-Rice Decoder with 8-bit Unary Decoding for Weight Compression in TinyML Applications.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023
2022
Microprocess. Microsystems, October, 2022
An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Accurate and Robust Malware Detection: Running XGBoost on Runtime Data From Performance Counters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
A Smart HW-Accelerator for Non-uniform Linear Interpolation of ML-Activation Functions.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022
Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2022
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021
Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2021
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the CODES/ISSS 2021, 2021
2020
Accurate Cost Estimation of Memory Systems Utilizing Machine Learning and Solutions from Computer Vision for Design Automation.
IEEE Trans. Computers, 2020
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Using Machine Learning for predicting area and Firmware metrics of hardware designs from abstract specifications.
Microprocess. Microsystems, 2019
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019
Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Quality Assessment of Generated Hardware Designs Using Statistical Analysis and Machine Learning.
Proceedings of the 8th International Workshop on Combinations of Intelligent Methods and Applications co-located with 30th International Conference on Artificial Intelligence Tools (ICTAI 2018), 2018
Analog fault simulation automation at schematic level with random sampling techniques.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping.
Proceedings of the International Symposium on Rapid System Prototyping, 2017
Python based framework for HDSLs with an underlying formal semantics: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017
2016
Speeding up safety verification by fault abstraction and simulation to transaction level.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Efficient handling of the fault space in functional safety analysis utilizing formal methods.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the Computer Safety, Reliability, and Security, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016
Proceedings of the 2016 Forum on Specification and Design Languages, 2016
Transformation of Failure Propagation Models into Fault Trees for Safety Evaluation Purposes.
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2016
Efficient Checkpointing-Based Safety-Verification Flow Using Compiled-Code Simulation.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
2015
The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems.
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
The semantic of the power intent format UPF: Consistent power modeling from system level to implementation.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
Proceedings of the 2013 International Symposium on System on Chip, 2013
Proceedings of the Computer Aided Systems Theory - EUROCAST 2013, 2013
2012
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
2011
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011
2010
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
Fast and accurate UML State Chart modeling using TLM<sup>+</sup> control flow abstraction.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010
Model reduction techniques for the formal verification of hardware dependent software.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007
Interactive presentation: Implementation of a transaction level assertion framework in SystemC.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006
Proceedings of the Forum on specification and Design Languages, 2006
Proceedings of the Forum on specification and Design Languages, 2006
2005
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005
2004
IEEE Des. Test Comput., 2004
Ein orthogonales Schema für die Klassifikation der Modellierungsabstraktion von digitalen Systemen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Memory Models for the Formal Verification of Assembler Code Using Bounded Model Checking.
Proceedings of the 7th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2004), 2004
Proceedings of the Forum on specification and Design Languages, 2004
Proceedings of the Forum on specification and Design Languages, 2004
Proceedings of the Forum on specification and Design Languages, 2004
2003
An Enhanced Environment for Multi-Level Simulation.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003
Incremental Design: A VHDL based Case Study.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003
An Approach for Mixed Coarse-Granular and Fine-Granular Re-Configurable Architectures.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Proceedings of the 40th Design Automation Conference, 2003
2002
Informationstechnik Tech. Inform., 2002
2001
Hardware-basierter Hardware-Entwurf.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001
2000
Eine flexible Simulationsumgebung für System-On-Chip Design (A Flexible Simulation Environment for System-On-Chip Design).
Informationstechnik Tech. Inform., 2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
VXML: VHDL Hardware Design Representation in XML.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000
Graphische Spezifikation und Analyse funktionaler Testabläufe mit MSCs der UML.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000
Proceedings of the 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, 2000
1999
A scalable multithreaded compiler front-end.
Proceedings of the Parallel Computing: Fundamentals & Applications, 1999
Proceedings of the 25th EUROMICRO '99 Conference, 1999
1998
1997
Proceedings of the 1997 Workshop on Engineering of Computer-Based Systems (ECBS '97), 1997
Proceedings of the 34st Conference on Design Automation, 1997
1996
J. Syst. Archit., 1996
Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionality.
Proceedings of the conference on European design automation, 1996
1995
Proceedings of the Proceedings EURO-DAC'95, 1995
Proceedings of the Proceedings EURO-DAC'95, 1995
Proceedings of the Proceedings EURO-DAC'95, 1995
1994
Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations.
Proceedings of the Proceedings EURO-DAC'94, 1994
1993
State look ahead technique for cycle optimization of interacting finite state Moore machines.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Proceedings of the European Design Automation Conference 1993, 1993
System-Level Specification and Design Using VHDL: A Case Study.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993
1992
Proceedings of the conference on European design automation, 1992
Proceedings of the conference on European design automation, 1992
Proceedings of the conference on European design automation, 1992