Bassel Soudan

Orcid: 0000-0001-8128-5498

According to our database1, Bassel Soudan authored at least 25 papers between 1989 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2024
Comparative study of ML models for IIoT intrusion detection: impact of data preprocessing and balancing.
Neural Comput. Appl., May, 2024

2023
A comprehensive survey on detection of sinkhole attack in routing over low power and Lossy network for internet of things.
Internet Things, July, 2023

2022
Artificial Intelligence and Statistical Techniques in Short-Term Load Forecasting: A Review.
CoRR, 2022

2020
Locating victims in hot environments using combined thermal and optical imaging.
Comput. Electr. Eng., 2020

2019
Robust nonlinear control and estimation of a Prrr robot System.
Int. J. Robotics Autom., 2019

2015
Filtering technique for high speed database sequence comparison.
Proceedings of the 9th IEEE International Conference on Semantic Computing, 2015

High Speed Database Sequence Comparison.
Proceedings of the 2015 International Conference on Soft Computing and Software Engineering, 2015

Computation Time Reduction to Speed-up the Database Searching Process.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

2011
Semi-random net reordering for reducing timing variations and improving signal integrity.
Microelectron. J., 2011

The effect of SRNR on timing characteristics of signal busses.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010
Reducing signal timing variations in inter-core busses.
Integr., 2010

Improving timing characteristics through Semi-Random Net Reordering.
Proceedings of the 5th International Design and Test Workshop, 2010

2009
Deploying FPGA self-configurable cell structure for micro crypto-functions.
Proceedings of the 14th IEEE Symposium on Computers and Communications (ISCC 2009), 2009

2008
Reconfigurable Cell Architecture for Systolic and Pipelined Computing Datapaths.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Globally verifiable clone-resistant device identity with mutual authentication.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Electronic mutation technology and secured identification.
Proceedings of the 9th International Symposium on Signal Processing and Its Applications, 2007

Bio-Inspired Electronic-Mutation with genetic properties for Secured Identification.
Proceedings of the 2007 ECSIS Symposium on Bio-inspired, 2007

2006
VLSI Design Exchange with Intellectual Property Protection in FPGA Environment Using both Secret and Public-Key Cryptography.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Fuzzy modular multiplication architecture and low complexity IPR-protection for FPGA technology.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Reducing Inductive Coupling Skew in Wide Global Signal Busses.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2005
Novel secret-key IPR protection in FPGA environment.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

2004
Managing inductive coupling in wide signal busses.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Reducing mutual inductance of wide signal busses through swizzling.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A protection mechanism for intellectual property rights (IPR) in FPGA design environment.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

1989
MIES: a microarchitecture design tool.
Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989


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