Rolf Ernst

According to our database1, Rolf Ernst authored at least 302 papers between 1988 and 2018.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2003, "For contributions to hardware and software co-design and embedded system design automation.".

Timeline

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Bibliography

2018
Synthesis of Monitors for Networked Systems With Heterogeneous Safety Requirements.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Platform-Centric Self-Awareness as a Key Enabler for Controlling Changes in CPS.
Proceedings of the IEEE, 2018

Self-Aware Network-on-Chip Control in Real-Time Systems.
IEEE Design & Test, 2018

Exploiting Execution Dynamics in Timing Analysis Using Job Sequences.
IEEE Design & Test, 2018

The Logical Execution Time Paradigm: New Perspectives for Multicore Systems (Dagstuhl Seminar 18092).
Dagstuhl Reports, 2018

Automated Driving: The Cyber-Physical Perspective.
IEEE Computer, 2018

Data-Age Analysis and Optimisation for Cause-Effect Chains in Automotive Control Systems.
Proceedings of the 13th IEEE International Symposium on Industrial Embedded Systems, 2018

Prediction of abnormal temporal behavior in real-time systems.
Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 2018

Weakly-Hard Real-Time Guarantees for Weighted Round-Robin Scheduling of Real-Time Messages.
Proceedings of the 23rd IEEE International Conference on Emerging Technologies and Factory Automation, 2018

Verifying Weakly-Hard Real-Time Properties of Traffic Streams in Switched Networks.
Proceedings of the 30th Euromicro Conference on Real-Time Systems, 2018

Design methodologies for enabling self-awareness in autonomous systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Cross-layer dependency analysis with timing dependence graphs.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Response-Time Analysis for Task Chains with Complex Precedence and Blocking Relations.
ACM Trans. Embedded Comput. Syst., 2017

Response Time Analysis for Sporadic Server Based Budget Scheduling in Real Time Virtualization Environments.
ACM Trans. Embedded Comput. Syst., 2017

Tackling the Bus Turnaround Overhead in Real-Time SDRAM Controllers.
IEEE Trans. Computers, 2017

Contracting challenges for system design and integration.
SIGBED Review, 2017

A system-level FPGA design methodology for video applications with weakly-programmable hardware components.
J. Real-Time Image Processing, 2017

Ensuring safety and efficiency in networks-on-chip.
Integration, 2017

Temporal Properties in Component-Based Cyber Physical Systems - Appendix.
CoRR, 2017

Providing throughput guarantees in mixed-criticality networks-on-chip.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Power and area evaluation of a fault-tolerant network-on-chip.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Temporal properties in automotive control software.
Proceedings of the 25th International Conference on Real-Time Networks and Systems, 2017

Finite ready queues as a mean for overload reduction in weakly-hard real-time systems.
Proceedings of the 25th International Conference on Real-Time Networks and Systems, 2017

Efficient Latency Guarantees for Mixed-Criticality Networks-on-Chip.
Proceedings of the 2017 IEEE Real-Time and Embedded Technology and Applications Symposium, 2017

Demo Abstract: Bounding Deadline Misses for Weakly-Hard Real-Time Systems Designed in CAPELLA.
Proceedings of the 2017 IEEE Real-Time and Embedded Technology and Applications Symposium, 2017

Designing Networks-on-Chip for High Assurance Real-Time Systems.
Proceedings of the 22nd IEEE Pacific Rim International Symposium on Dependable Computing, 2017

Replica-Aware Co-Scheduling for Mixed-Criticality.
Proceedings of the 29th Euromicro Conference on Real-Time Systems, 2017

Budgeting Under-Specified Tasks for Weakly-Hard Real-Time Systems.
Proceedings of the 29th Euromicro Conference on Real-Time Systems, 2017

Real-time communication analysis for Networks-on-Chip with backpressure.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Contract-based integration of automotive control software.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Self-awareness in autonomous automotive systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Bounding deadline misses in weakly-hard real-time systems with task dependencies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Architecting high-speed command schedulers for open-row real-time SDRAM controllers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Exploiting sporadic servers to provide budget scheduling for ARINC653 based real-time virtualization environments.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Adaptive load distribution in mixed-critical Networks-on-Chip.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Guest Editorial for Special Issue of ESWEEK 2015.
ACM Trans. Embedded Comput. Syst., 2016

Formal timing analysis of CAN-to-Ethernet gateway strategies in automotive networks.
Real-Time Systems, 2016

Special issue of the Euromicro Conference on Real-Time Systems (ECRTS).
Real-Time Systems, 2016

Mixed Criticality Systems - A History of Misconceptions?
IEEE Design & Test, 2016

Report of the 2015 Embedded Systems Week (ESWEEK).
IEEE Design & Test, 2016

System-level timing feasibility test for cyber-physical automotive systems.
Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

Supporting Suspension-based Locking Mechanisms for Real-Time Networks-on-chip.
Proceedings of the 24th International Conference on Real-Time Networks and Systems, 2016

Demo Abstract: Response-Time Analysis for Task Chains in Communicating Threads with pyCPA.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

Response-Time Analysis for Task Chains in Communicating Threads.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

Safe and dynamic traffic rate control for networks-on-chips.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

Formal worst-case performance analysis of time-sensitive Ethernet with frame preemption.
Proceedings of the 21st IEEE International Conference on Emerging Technologies and Factory Automation, 2016

Zero-time communication for automotive multi-core systems under SPP scheduling.
Proceedings of the 21st IEEE International Conference on Emerging Technologies and Factory Automation, 2016

Multi-Path Scheduling for Multimedia Traffic in Safety Critical On-chip Network.
Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016

Minimizing DRAM Rank Switching Overhead for Improved Timing Bounds and Performance.
Proceedings of the 28th Euromicro Conference on Real-Time Systems, 2016


Formal worst-case timing analysis of Ethernet TSN's burst-limiting shaper.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Formal analysis based evaluation of software defined networking for time-sensitive Ethernet.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Providing formal latency guarantees for ARQ-based protocols in Networks-on-Chip.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Handling complex dependencies in system design.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Slack-based resource arbitration for real-time Networks-on-Chip.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Guarantees for runnable entities with heterogeneous real-time requirements.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Invited - Towards fail-operational ethernet based in-vehicle networks.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Self-aware systems for the internet-of-things.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Conquering MPSoC complexity with principles of a self-aware information processing factory.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Dynamic admission control for real-time networks-on-chips.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Multi-layer software reliability for unreliable hardware.
it - Information Technology, 2015

Formal worst-case timing analysis of Ethernet TSN's time-aware and peristaltic shapers.
Proceedings of the 2015 IEEE Vehicular Networking Conference, 2015

Real-time DRAM throughput guarantees for latency sensitive mixed QoS MPSoCs.
Proceedings of the 10th IEEE International Symposium on Industrial Embedded Systems, 2015

Dynamic Control for Mixed-Critical Networks-on-Chip.
Proceedings of the 2015 IEEE Real-Time Systems Symposium, 2015

Improved DRAM Timing Bounds for Real-Time DRAM Controllers with Read/Write Bundling.
Proceedings of the 2015 IEEE Real-Time Systems Symposium, 2015

Flexible TDM-based resource management in on-chip networks.
Proceedings of the 23rd International Conference on Real Time Networks and Systems, 2015

An approach for physical topology exploration in wired bus networks.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An Extensible Autonomous Reconfiguration Framework for Complex Component-Based Embedded Systems.
Proceedings of the 2015 IEEE International Conference on Autonomic Computing, 2015

Parallel feature extraction and heterogeneous object-detection for multi-camera driver assistance systems.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Improved Deadline Miss Models for Real-Time Systems Using Typical Worst-Case Analysis.
Proceedings of the 27th Euromicro Conference on Real-Time Systems, 2015

Worst-case communication time analysis of networks-on-chip with shared virtual channels.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Designing time partitions for real-time hypervisor with sufficient temporal independence.
Proceedings of the 52nd Annual Design Automation Conference, 2015

The shift to multicores in real-time and safety-critical systems.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

2014
Building timing predictable embedded systems.
ACM Trans. Embedded Comput. Syst., 2014

Supervised sharing of virtual channels in Networks -on-Chip.
Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems, 2014

Formal timing analysis of automatic repeat request for switched real-time networks.
Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems, 2014

A mixed critical memory controller using bank privatization and fixed priority scheduling.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

FMEA-based analysis of a Network-on-Chip for mixed-critical systems.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Specifying a middleware for distributed embedded vehicle control systems.
Proceedings of the IEEE International Conference on Vehicular Electronics and Safety, 2014

Efficient 3D triangulation in hardware for dense structure-from-motion in low-speed automotive scenarios.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Extending typical worst-case analysis using response-time dependencies to bound deadline misses.
Proceedings of the 2014 International Conference on Embedded Software, 2014

Failure analysis of a network-on-chip for real-time mixed-critical systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Typical Worst Case Response-Time Analysis and its Use in Automotive Network Design.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Sufficient Temporal Independence and Improved Interrupt Latencies in a Real-Time Hypervisor.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Exploiting Shaper Context to Improve Performance Bounds of Ethernet AVB Networks.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Workload-aware shaping of shared resource accesses in mixed-criticality systems.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Improving formal timing analysis of switched ethernet by exploiting traffic stream correlations.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Distributed Priority Assignment in Real-Time Systems.
Proceedings of the Embedded Systems Development, From Functional Models to Implementations, 2014

2013
Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor.
IEEE Trans. VLSI Syst., 2013

MORPHEUS: A heterogeneous dynamically reconfigurable platform for designing highly complex embedded systems.
ACM Trans. Embedded Comput. Syst., 2013

Compositional performance analysis with improved analysis techniques for obtaining viable end-to-end latencies in distributed embedded systems.
STTT, 2013

Monitoring of Workload Arrival Functions for Mixed-Criticality Systems.
Proceedings of the IEEE 34th Real-Time Systems Symposium, 2013

IDAMC: A NoC for mixed criticality systems.
Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

Towards a Certifiable Integration of SRAM-Based FPGAs in Safety-Critical Automotive Systems.
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

Exploration of FPGA-based dense block matching for motion estimation and stereo vision on a single chip.
Proceedings of the 2013 IEEE Intelligent Vehicles Symposium (IV), 2013

Message from the program co-chairs.
Proceedings of the International Conference on Embedded Software, 2013

Response-Time Analysis of Parallel Fork-Join Workloads with Real-Time Constraints.
Proceedings of the 25th Euromicro Conference on Real-Time Systems, 2013

Formal analysis of sporadic bursts in real-time systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Sensitivity analysis for arbitrary activation patterns in real-time systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Timing analysis of multi-mode applications on AUTOSAR conform multi-core systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Stochastic response-time guarantee for non-preemptive, fixed-priority scheduling under errors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Improved formal worst-case timing analysis of weighted round robin scheduling for Ethernet.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Multi-mode monitoring for mixed-criticality real-time systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

2012
Response-time analysis of the flexray dynamic segment under consideration of slot-multiplexing.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

Response-time analysis for non-preemptive scheduling in multi-core systems with shared resources.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

Formal worst-case timing analysis of Ethernet topologies with strict-priority and AVB switching.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

Monitoring Arbitrary Activation Patterns in Real-Time Systems.
Proceedings of the 33rd IEEE Real-Time Systems Symposium, 2012

Generalized Weakly-Hard Constraints.
Proceedings of the Leveraging Applications of Formal Methods, Verification and Validation. Applications and Case Studies, 2012

IDAMC: A Many-Core Platform with Run-Time Monitoring for Mixed-Criticality.
Proceedings of the 14th International IEEE Symposium on High-Assurance Systems Engineering, 2012

Designing an Analyzable and Resilient Embedded Operating System.
Proceedings of the Informatik 2012, 2012

Mixed critical system design and analysis.
Proceedings of the 12th International Conference on Embedded Software, 2012

Deriving Monitoring Bounds for Distributed Real-Time Systems.
Proceedings of the 24th Euromicro Conference on Real-Time Systems, 2012

Optimizing performance analysis for synchronous dataflow graphs with shared resources.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A high-performance dense block matching solution for automotive 6D-vision.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Using timing analysis for the design of future switched based Ethernet automotive networks.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Formal analysis of sporadic overload in real-time systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Challenges and new trends in probabilistic timing analysis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Probabilistic response time bound for CAN messages with arbitrary deadlines.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Internet-of-energy: combining embedded computing and communication for the smart grid.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Trends in automotive embedded systems.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

System Level Performance Analysis for Real-Time Multi-Core and Network Architectures.
Proceedings of the Advances in Real-Time Systems (to Georg Färber on the occasion of his appointment as Professor Emeritus at TU München after leading the Lehrstuhl für Realzeit-Computersysteme for 34 illustrious years)., 2012

Institut für Datentechnik und Kommunikationsnetze.
Proceedings of the 40 Jahre Informatik an der Technischen Universität Braunschweig, 1972, 2012

2011
Mastering MPSoCs for Mixed-critical Applications.
IPSJ Trans. System LSI Design Methodology, 2011

The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform.
International Journal of Parallel Programming, 2011

Contract-based dynamic task management for mixed-criticality systems.
Proceedings of the Industrial Embedded Systems (SIES), 2011

Admission control and self-configuration in the EPOC framework.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Utilizing Hidden Markov Models for Formal Reliability Analysis of Real-Time Communication Systems with Errors.
Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing, 2011

A Lazy Algorithm for Distributed Priority Assignment in Real-Time Systems.
Proceedings of the 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2011

Bounding mode change transition latencies for multi-mode real-time distributed applications.
Proceedings of the IEEE 16th Conference on Emerging Technologies & Factory Automation, 2011

Real-time communication analysis for networks with two-stage arbitration.
Proceedings of the 11th International Conference on Embedded Software, 2011


Reliability analysis for MPSoCs with mixed-critical, hard real-time constraints.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

The EPOC Architecture - Enabling Evolution Under Hard Constraints.
Proceedings of the Organic Computing - A Paradigm Shift for Complex Systems, 2011

2010
Real-time performance analysis of multiprocessor systems with shared memory.
ACM Trans. Embedded Comput. Syst., 2010

Editorial: Model-driven embedded-system design.
ACM Trans. Embedded Comput. Syst., 2010

Estimating and Mitigating Design Risk in a Flexible Distributed Design Process.
Embedded Systems Letters, 2010

Back Suction: Service Guarantees for Latency-Sensitive On-chip Networks.
Proceedings of the NOCS 2010, 2010

Consistency Challenges in Self-Organizing Distributed Hard Real-Time Systems.
Proceedings of the 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2010

Safety, Efficiency and Autonomy - Mastering Conflicting Trends in Embedded Systems Design.
Proceedings of the Distributed, Parallel and Biologically Inspired Systems, 2010

A Scalable, High-Performance Motion Estimation Application for a Weakly-Programmable FPGA Architecture.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

A Polynomial-Time Algorithm for Computing Response Time Bounds in Static Priority Scheduling Employing Multi-linear Workload Bounds.
Proceedings of the 22nd Euromicro Conference on Real-Time Systems, 2010

Application-specific memory performance of a heterogeneous reconfigurable architecture.
Proceedings of the Design, Automation and Test in Europe, 2010

Bounding the shared resource load for the performance analysis of multiprocessor systems.
Proceedings of the Design, Automation and Test in Europe, 2010

Exploiting inter-event stream correlations between output event streams of non-preemptively scheduled tasks.
Proceedings of the Design, Automation and Test in Europe, 2010

A software update service with self-protection capabilities.
Proceedings of the Design, Automation and Test in Europe, 2010

Efficient throughput-guarantees for latency-sensitive networks-on-chip.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Response Time Analysis in Multicore ECUs with Shared Resources.
IEEE Trans. Industrial Informatics, 2009

Application development with the FlexWAFE real-time stream processing architecture for FPGAs.
ACM Trans. Embedded Comput. Syst., 2009

System Level Performance Analysis for Real-Time Automotive Multicore and Network Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Influence of different abstractions on the performance analysis of distributed hard real-time systems.
Design Autom. for Emb. Sys., 2009

Dependency-aware stochastic analysis of chained execution times.
Proceedings of the IEEE Fourth International Symposium on Industrial Embedded Systems, 2009

Probabilistic Network Loads with Dependencies and the Effect on Queue Sojourn Times.
Proceedings of the Quality of Service in Heterogeneous Networks, 2009

Reliability Analysis of Single Bus Communication with Real-Time Requirements.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture.
Proceedings of the Design, Automation and Test in Europe, 2009

Learning early-stage platform dimensioning from late-stage timing verification.
Proceedings of the Design, Automation and Test in Europe, 2009

Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources.
Proceedings of the Design, Automation and Test in Europe, 2009

Panel session - Multicore, will Startups drive innovation?
Proceedings of the Design, Automation and Test in Europe, 2009

A link arbitration scheme for quality of service in a latency-optimized network-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2009

A recursive approach to end-to-end path latency computation in heterogeneous multiprocessor systems.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
Sensitivity analysis of complex embedded real-time systems.
Real-Time Systems, 2008

A bandwidth optimized SDRAM controller for the MORPHEUS reconfigurable architecture.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Modelling and designing reliable on-chip-communication devices in MPSoCs with real-time requirements.
Proceedings of 13th IEEE International Conference on Emerging Technologies and Factory Automation, 2008

Construction and Deconstruction of Hierarchical Event Streams with Multiple Hierarchical Layers.
Proceedings of the 20th Euromicro Conference on Real-Time Systems, 2008

Modeling Event Stream Hierarchies with Hierarchical Event Models.
Proceedings of the Design, Automation and Test in Europe, 2008

Methods, Tools and Standards for the Analysis, Evaluation and Design of Modern Automotive Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008

Formal Methods in System and MpSoC Performance Analysis and Optimisation.
Proceedings of the Design, Automation and Test in Europe, 2008

Providing accurate event models for the analysis of heterogeneous multiprocessor systems.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

Reliable performance analysis of a multicore multithreaded system-on-chip.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

Distributed Performance Control in Organic Embedded Systems.
Proceedings of the Autonomic and Trusted Computing, 5th International Conference, 2008

2007
Scalable precision cache analysis for real-time software.
ACM Trans. Embedded Comput. Syst., 2007

A High-End Real-Time Digital Film Processing Reconfigurable Platform.
EURASIP J. Emb. Sys., 2007

Scenario Aware Analysis for Complex Event Models and Distributed Systems.
Proceedings of the 28th IEEE Real-Time Systems Symposium (RTSS 2007), 2007

Multi-dimensional Robustness Optimization in Heterogeneous Distributed Embedded Systems.
Proceedings of the 13th IEEE Real-Time and Embedded Technology and Applications Symposium, 2007

Improved Output Jitter Calculation for Compositional Performance Analysis of Distributed Systems.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Automotive System Optimization using Sensitivity Analysis.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Efficient priority optimization in complex distributed embedded systems through search space adaptation.
Proceedings of the Genetic and Evolutionary Computation Conference, 2007

Influence of different system abstractions on the performance analysis of distributed real-time systems.
Proceedings of the 7th ACM & IEEE International conference on Embedded software, 2007

Methods for multi-dimensional robustness optimization in complex embedded systems.
Proceedings of the 7th ACM & IEEE International conference on Embedded software, 2007

Performance analysis of complex systems by integration of dataflow graphs and compositional performance analysis.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Automotive Software Integration.
Proceedings of the 44th Design Automation Conference, 2007

FlexWAFE - A High-end Real-Time Stream Processing Library for FPGAs.
Proceedings of the 44th Design Automation Conference, 2007

Improved response time analysis of tasks scheduled under preemptive Round-Robin.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Combined approach to system level performance analysis of embedded systems.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Automotive networks: are new busses and gateways the answer or just another challenge?
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
A framework for modular analysis and exploration of heterogeneous embedded systems.
Real-Time Systems, 2006

A Framework for the Busy Time Calculation of Multiple Correlated Events.
Proceedings of the 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, 2006

Scheduling Anomaly Detection and Optimization for Distributed Systems with Preemptive Task-Sets.
Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2006), 2006

VLSI Design Exchange with Intellectual Property Protection in FPGA Environment Using both Secret and Public-Key Cryptography.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Real-Time Property Verification in Organic Computing Systems.
Proceedings of the Leveraging Applications of Formal Methods, 2006

Cost-Efficient Worst-Case Execution Time Analysis in Industrial Practice.
Proceedings of the Leveraging Applications of Formal Methods, 2006

Real-time Management in Emergent Systems.
Proceedings of the Informatik 2006, 2006

Worst case timing analysis of input dependent data cache behavior.
Proceedings of the 18th Euromicro Conference on Real-Time Systems, 2006

A Formal Approach to Multi-Dimensional Sensitivity Analysis of Embedded Real-Time Systems.
Proceedings of the 18th Euromicro Conference on Real-Time Systems, 2006

How OEMs and suppliers can face the network integration challenges.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Improved offset-analysis using multiple timing-references.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

FlexFilm - an Image Processor for Digital Film Processing.
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

Integrated analysis of communicating tasks in MPSoCs.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

A formal approach to robustness maximization of complex heterogeneous embedded systems.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Methods for power optimization in distributed embedded systems with real-time requirements.
Proceedings of the 2006 International Conference on Compilers, 2006

2005
Performance analysis for complex embedded applications.
IJES, 2005

Analysis of Memory Latencies in Multi-Processor Systems.
Proceedings of the 5th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, 2005

Applying Sensitivity Analysis in Real-Time Distributed Systems.
Proceedings of the 11th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2005), 2005

Early Architecture Exploration with SymTA/S.
Proceedings of the Dagstuhl-Workshop MBEES: Modellbasierte Entwicklung eingebetteter Systeme I, 2005

Scalable precision cache analysis for preemptive scheduling.
Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, 2005

From Model to Requirements: Pattern-Based Analysis in Distributed Development of Embedded Systems.
Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005

Dynamic voltage scaling for the schedulability of jitter-constrained real-time embedded systems.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme.
Proceedings of the INFORMATIK 2005, 2005

An FPGA based SDRAM controller with complex QoS scheduling and traffic shaping (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay.
Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS 2005), 2005

Context Sensitive Performance Analysis of Automotive Applications.
Proceedings of the 2005 Design, 2005

Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes.
Proceedings of the 2005 Design, 2005

Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-Dependencies.
Proceedings of the 2005 Design, 2005

TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques.
Proceedings of the 2005 Design, 2005

Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements.
Proceedings of the 42nd Design Automation Conference, 2005

An Image Processor for Digital Film.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Interval-based analysis in embedded system design.
Mathematics and Computers in Simulation, 2004

Design Space Exploration and System Optimization with SymTA/S-Symbolic Timing Analysis for Systems.
Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 2004

Calculating Task Output Event Models to Reduce Distributed System Cost.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Multiple process execution in cache related preemption delay analysis.
Proceedings of the EMSOFT 2004, 2004

Context-Aware Performance Analysis for Efficient Embedded System Design.
Proceedings of the 2004 Design, 2004

2003
Putting It All Together.
ACM Queue, 2003

A Formal Approach to MpSoC Performance Verification.
IEEE Computer, 2003

Scheduling Analysis Integration for Heterogeneous Multiprocessor SoC.
Proceedings of the 24th IEEE Real-Time Systems Symposium (RTSS 2003), 2003

Certifiable Software-Integration for Engine Electronics.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

Safe Automotive Software Development.
Proceedings of the 2003 Design, 2003

Formal Methods for Integration of Automotive Software.
Proceedings of the 2003 Design, 2003

Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals.
Proceedings of the 40th Design Automation Conference, 2003

The future of system-level design: can we find the right solutions to the right problems at the right time?
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
SPI - a system model for heterogeneously specified embedded systems.
IEEE Trans. VLSI Syst., 2002

Hybrid Cache Analysis in Running Time Verification of Embedded Software.
Design Autom. for Emb. Sys., 2002

Flexibility/Cost-Tradeoffs of Platform-Based Systems.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Local Constraint Derivation for Platform-Based Design.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2002

Modellierung rekonfigurierbarer Systemarchitekturen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2002

Bottom-Up Performance Analysis of HW/SW Platforms.
Proceedings of the Design and Analysis of Distributed Embedded Systems, IFIP 17<sup>th</sup> World Computer Congress, 2002

Event Model Interfaces for Heterogeneous System Analysis.
Proceedings of the 2002 Design, 2002

System Design for Flexibility.
Proceedings of the 2002 Design, 2002

Associative caches in formal software timing analysis.
Proceedings of the 39th Design Automation Conference, 2002

Model composition for scheduling analysis in platform design.
Proceedings of the 39th Design Automation Conference, 2002

Transformation of SDL specifications for system-level timing analysis.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Readings in hardware / software co-design.
Morgan Kaufmann, ISBN: 978-1-55860-702-6, 2002

2001
Path clustering in software timing analysis.
IEEE Trans. VLSI Syst., 2001

FunState-an internal design representation for codesign.
IEEE Trans. VLSI Syst., 2001

An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques.
IEEE Trans. VLSI Syst., 2001

Execution cost interval refinement in static software analysis.
Journal of Systems Architecture, 2001

Interval-Based Analysis of Software Processes.
Proceedings of The Workshop on Languages, 2001

Combining complex event models and timing constraints.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

Combining Languages in Embedded System Design.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

2000
Das DFG-Schwerpunktprogramm 1020 (Research Priority Program 1020 of the German "Deutsche Forschungsgemeinschaft").
it+ti - Informationstechnik und Technische Informatik, 2000

Rapid Prototyping von integrierten Steuerungssystemen.
it+ti - Informationstechnik und Technische Informatik, 2000

Intervals in Software Execution Cost Analysis.
Proceedings of the 13th International Symposium on System Synthesis, 2000

A Transformational Approach to Constraint Relaxation of a Time-driven Simulation Model.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Data flow based cache prediction using local simulation.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

A Reconfigurable Hardware Platform for Digital Real-Time Signal Processing in Television Studios.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

The Future of Flexible HW Platform Architectures Panel Discussion.
Proceedings of the 2000 Design, 2000

embedded system design with multiple languages: embedded tutorial.
Proceedings of ASP-DAC 2000, 2000

1999
Process Versions in Rapid Prototyping.
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

SPI -- An Internal Representation for Heterogeneously Specified Embedded Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1999

FunState - an internal design representation for codesign.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Improved interconnect sharing by identity operation insertion.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

System level design and debug of high-performance embedded media systems (tutorial).
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Multi-Language System Design.
Proceedings of the 1999 Design, 1999

Representation of Function Variants for Embedded System Optimization and Synthesis.
Proceedings of the 36th Conference on Design Automation, 1999

Scheduling hardware/software systems using symbolic techniques.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

Using Adaptive Layout Calculation to Handle the Visual Chaos in GUIs.
Proceedings of the Computer-Aided Design of User Interfaces II, 1999

1998
Codesign of Embedded Systems: Status and Trends.
IEEE Design & Test of Computers, 1998

Representation of process mode correlation for scheduling.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Combining multiple models of computation for scheduling and allocation.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

High-Level Estimation Techniques for Usage in Hardware/Software Co-Design.
Proceedings of the ASP-DAC '98, 1998

1997
An Adaptive Window Management System.
Proceedings of the Human-Computer Interaction, 1997

Embedded program timing analysis based on path clustering and architecture classification.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

A processor-coprocessor architecture for high end video applications.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

Rapid Prototyping für integrierte Steuerungssysteme mit harten Zeitbedingungen.
Proceedings of the Informatik '97, 1997

Register synthesis for speculative computation.
Proceedings of the European Design and Test Conference, 1997

A Hardware/Software Partitioner Using a Dynamically Determined Granularity.
Proceedings of the 34st Conference on Design Automation, 1997

An Event-Driven Multi-Threading Architecture for Embedded Systems.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

An Approach to Mixed Systems Co-Synthesis.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996
The COSYMA environment for hardware/software cosynthesis of small embedded systems.
Microprocessors and Microsystems - Embedded Hardware Design, 1996

The Interplay of Run-Time Estimation and Granularity in HW/SW Partitioning.
Proceedings of the Forth International Workshop on Hardware/Software Codesign, 1996

1995
An Approach to Automatic Display Layout Using Combinatorial Optimization Algorithms.
Softw., Pract. Exper., 1995

Das Automatisierte Bildschirmlayout.
Inform., Forsch. Entwickl., 1995

A prototyping system for verification and evaluation in hardware-software cosynthesis.
Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP '95), 1995

A path-based technique for estimating hardware runtime in HW/SW-cosynthesis.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Research report: improving browsing in information by the automatic display layout.
Proceedings of the IEEE Symposium On Information Visualization 1995, 1995

Scalable performance scheduling for hardware-software cosynthesis.
Proceedings of the Proceedings EURO-DAC'95, 1995

Combining MBP-speculative computation and loop pipelining in high-level synthesis.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
The Dynamic Screen - Beyond the Limits of Traditional Graphic User Interfaces.
Proceedings of the Technology and Foundations - Information Processing '94, Volume 1, Proceedings of the IFIP 13th World Computer Congress, Hamburg, Germany, 28 August, 1994

Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

FPGA Based Prototyping for Verification and Evaluation in Hardware-Software Cosynthesis.
Proceedings of the Field-Programmable Logic, 1994

An approach to the adaptation of estimated cost parameters in the COSYMA system.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

1993
Experiments with low-level speculative computation based on multiple branch prediction.
IEEE Trans. VLSI Syst., 1993

Hardware-Software Cosynthesis for Microcontrollers.
IEEE Design & Test of Computers, 1993

Automatic Display Layout in Window Oriented User Interfaces.
Proceedings of the Interfaces in Industrial Systems for Production Engineering, 1993

Fast Timing Analysis for Hardware-Software Co-Synthesis.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Speculative Computation for Coprocessor Synthesis.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992
Verbesserung der Benutzeroberfläche von CAD-Systemen durch automatisches Bildschirmlayout.
Proceedings of the CAD '92: Neue Konzepte zur Realisierung anwendungsorientierter CAD-Systeme, 1992

1991
Simulation-Based Verification for High-Level Synthesis.
IEEE Design & Test of Computers, 1991

Fault Tolerant VLSI Design with Functional Block Redundancy.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990
Simulation based verification of register-transfer level behavioral synthesis tools.
Proceedings of the European Design Automation Conference, 1990

1989
TSG: A Test System Generator for Debugging and Regression Test of High-Level Behavioral Synthesis Tools.
Proceedings of the Proceedings International Test Conference 1989, 1989

1988
Ein neuartiges Steuerflusskonzept für vielstufige Pipelines in integrierten Signalprozessoren und das Modell eines Signalprozessors als Beispiel für seinen Einsatz.
PhD thesis, 1988


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