Behrooz Parhami

According to our database1, Behrooz Parhami authored at least 149 papers between 1972 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1997, "For contributions to the design of high-performance digital systems through arithmetic algorithms and highly parallel architectures.".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

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Bibliography

2019
Tabular Computation.
Proceedings of the Encyclopedia of Big Data Technologies., 2019

Parallel Processing with Big Data.
Proceedings of the Encyclopedia of Big Data Technologies., 2019

Energy Implications of Big Data.
Proceedings of the Encyclopedia of Big Data Technologies., 2019

Data Replication and Encoding.
Proceedings of the Encyclopedia of Big Data Technologies., 2019

Data Longevity and Compatibility.
Proceedings of the Encyclopedia of Big Data Technologies., 2019

Computer Architecture for Big Data.
Proceedings of the Encyclopedia of Big Data Technologies., 2019

Virtual Network Embedding Through Graph Eigenspace Alignment.
IEEE Trans. Network and Service Management, 2019

2018
Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies.
T-SUSC, 2018

Symmetric Agency Graphs Facilitate and Improve the Quality of Virtual Network Embedding.
Symmetry, 2018

Parallelism in Computer Arithmetic: A Historical Perspective (Invited Paper).
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Analog Representations in Digital Arithmetic: A Review.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

The Return of Table-Based Computing.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2016
Low Acceptance Rates of Conference Papers Considered Harmful.
IEEE Computer, 2016

A Formulation of Fast Carry Chains Suitable for Efficient Implementation with Majority Elements.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

A theoretical analysis of square versus rectangular component multipliers in recursive multiplication.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016

2015
Interconnection Networks with Hypercubic Skeletons.
Journal of Interconnection Networks, 2015

Amdahl's Reliability Law: A Simple Quantification of the Weakest-Link Phenomenon.
IEEE Computer, 2015

Digital Arithmetic in Nature: Continuous-Digit RNS.
Comput. J., 2015

2013
Arithmetic with binary-encoded balanced ternary numbers.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

A logarithmic approach to energy-efficient GPU arithmetic for mobile devices.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

Logarithmic arithmetic as an alternative to floating-point: A review.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
A Class of Data-Center Network Models Offering Symmetry, Scalability, and Reliability.
Parallel Processing Letters, 2012

Nearly Optimal Node-to-Set Parallel Routing in OTIS Networks.
Journal of Interconnection Networks, 2012

Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits.
IET Computers & Digital Techniques, 2012

2011
On necessary conditions for scale-freedom in complex networks, with applications to computer communication systems.
Int. J. Systems Science, 2011

Biswapped networks: a family of interconnection architectures with advantages over swapped or OTIS networks.
Int. J. Comput. Math., 2011

On building general modular adders from standard binary arithmetic components.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010
Construction of vertex-disjoint paths in alternating group networks.
The Journal of Supercomputing, 2010

Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value.
IEEE Trans. Computers, 2010

Fully symmetric swapped networks based on bipartite cluster connectivity.
Inf. Process. Lett., 2010

2009
Swapped (OTIS) Networks Built of Connected Basis Networks Are Maximally Fault Tolerant.
IEEE Trans. Parallel Distrib. Syst., 2009

Motivating Computer Engineering Freshmen Through Mathematical and Logical Puzzles.
IEEE Trans. Education, 2009

Efficient Hamming Weight Comparators for Binary Vectors Based on Accumulative and Up/Down Parallel Counters.
IEEE Trans. on Circuits and Systems, 2009

Load-balancing on swapped or OTIS networks.
J. Parallel Distrib. Comput., 2009

On routing and diameter of metacyclic graphs.
Int. J. Comput. Math., 2009

Puzzling Problems in Computer Engineering.
IEEE Computer, 2009

On General Laws of Complex Networks.
Proceedings of the Complex Sciences, 2009

Unified Approach to the Design of Modulo-(2n +/- 1) Adders Based on Signed-LSB Representation of Residues.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

2008
Comments on "Low Diameter Interconnections for Routing in High-Performance Parallel Systems, " with Connections and Extensions to Arc Coloring of Coset Graphs.
IEEE Trans. Computers, 2008

Periodically Regular Chordal Rings are Preferable to Double-Ring Networks.
Journal of Interconnection Networks, 2008

On isomorphisms and similarities between generalized Petersen networks and periodically regular chordal rings.
Inf. Process. Lett., 2008

Constant-time addition with hybrid-redundant numbers: Theory and implementations.
Integration, 2008

Double-least-significant-bits 2's-complement number representation scheme with bitwise complementation and symmetric range.
IET Circuits, Devices & Systems, 2008

A puzzle-based seminar for computer engineering freshmen.
Computer Science Education, 2008

2007
A Group Construction Method with Applications to Deriving Pruned Interconnection Networks.
IEEE Trans. Parallel Distrib. Syst., 2007

Structural properties of Cayley digraphs with applications to mesh and pruned torus interconnection networks.
J. Comput. Syst. Sci., 2007

Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic.
IET Circuits, Devices & Systems, 2007

Further mathematical properties of Cayley digraphs applied to hexagonal and honeycomb meshes.
Discrete Applied Mathematics, 2007

Biswapped Networks and Their Topological Properties.
Proceedings of the 8th ACIS International Conference on Software Engineering, 2007

Distributed Interval Voting with Node Failures of Various Types.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Extended Clustering Coefficients of Small-World Networks.
Proceedings of the Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27, 2007

An Efficient Construction of Node Disjoint Paths in OTIS Networks.
Proceedings of the Advanced Parallel Processing Technologies, 7th International Symposium, 2007

2006
An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding.
VLSI Signal Processing, 2006

Internode Distance and Optimal Routing in a Class of Alternating Group Networks.
IEEE Trans. Computers, 2006

Cayley graphs as models of deterministic small-world networks.
Inf. Process. Lett., 2006

Further Properties of Cayley Digraphs and Their Applications to Interconnection Networks.
Proceedings of the Theory and Applications of Models of Computation, 2006

2005
Performance, Algorithmic, and Robustness Attributes of Perfect Difference Networks.
IEEE Trans. Parallel Distrib. Syst., 2005

Perfect Difference Networks and Related Interconnection Structures for Parallel and Distributed Systems.
IEEE Trans. Parallel Distrib. Syst., 2005

Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems.
IEEE Trans. on Circuits and Systems, 2005

Swapped interconnection networks: Topological, performance, and robustness attributes.
J. Parallel Distrib. Comput., 2005

Diameter formulas for a class of undirected double-loop networks.
Journal of Interconnection Networks, 2005

The Hamiltonicity of swapped (OTIS) networks built of Hamiltonian component networks.
Inf. Process. Lett., 2005

Some mathematical properties of cayley digraphs with applications to interconnection network design.
Int. J. Comput. Math., 2005

Application of Perfect Difference Sets to the Design of Efficient and Robust Interconnection Networks.
Proceedings of the 2005 International Conference on Communications in Computing, 2005

Chordal Rings Based on Symmetric Odd-Radix Number Systems.
Proceedings of the 2005 International Conference on Communications in Computing, 2005

2004
Comparing four classes of torus-based parallel architectures: Networkparameters and communication performance.
Mathematical and Computer Modelling, 2004

Incomplete k-ary n-cube and its derivatives.
J. Parallel Distrib. Comput., 2004

Hexagonal and Pruned Torus Networks as Cayley Graphs.
Proceedings of the International Conference on Communications in Computing, 2004

Some Properties of Swapped Interconnection Networks.
Proceedings of the International Conference on Communications in Computing, 2004

2003
Tight Upper Bounds on the Minimum Precision Required of the Divisor and the Partial Remainder in High-Radix Division.
IEEE Trans. Computers, 2003

Parallel Architectures and Adaptation Algorithms for Programmable FIR Digital Filters With Fully Pipelined Data and Control Flows.
J. Inf. Sci. Eng., 2003

Some Conclusions on Cayley Digraphs and Their Applications to Interconnection Networks.
Proceedings of the Grid and Cooperative Computing, Second International Workshop, 2003

2002
ART: Robustness of Meshes and Tori for Parallel and Distributed Computation.
Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002

2001
Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization.
VLSI Signal Processing, 2001

A Unified Formulation of Honeycomb and Diamond Networks.
IEEE Trans. Parallel Distrib. Syst., 2001

Approach to component based synthesis of fault tolerant software.
Informatica (Slovenia), 2001

RACE: A Software-Based Fault Tolerance Scheme for Systematically Transforming Ordinary Algorithms to Robust Algorithms.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

On the VLSI Area and Bisection Width of Star Graphs and Hierarchical Cubic Networks.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

Parallel Algorithms for Index-Permutation Graphs - An Extension of Cayley Graphs for Multiple Chip-Multiprocessors (MCMP).
Proceedings of the 2001 International Conference on Parallel Processing, 2001

2000
VLSI layout and packaging of butterfly networks.
Proceedings of the Twelfth annual ACM Symposium on Parallel Algorithms and Architectures, 2000

Extended-Fault Diameter of Mesh Networks.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Characterization and Generalization of Honeycomb and Diamond Networks.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Multilayer VLSI Layout for Interconnection Networks.
Proceedings of the 2000 International Conference on Parallel Processing, 2000

Computer arithmetic - algorithms and hardware designs.
Oxford University Press, ISBN: 978-0-19-512583-2, 2000

1999
Scalability of Programmable FIR Digital Filters.
VLSI Signal Processing, 1999

Correction to 'Periodically Regular Chordal Rings'.
IEEE Trans. Parallel Distrib. Syst., 1999

Periodically Regular Chordal Rings.
IEEE Trans. Parallel Distrib. Syst., 1999

Data-Driven Control Scheme for Linear Arrays: Application to a Stable Insertion Sorter.
IEEE Trans. Parallel Distrib. Syst., 1999

The Recursive Grid Layout Scheme for VLSI Layout of Hierarchical Networks.
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999

2.5n-Step Sorting on n*n Meshes in the Presence of o(sqrt(n)) Worst-Case Faults.
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999

Routing and Embeddings in Cyclic Petersen Networks: An Efficient Extension of the Petersen Graph.
Proceedings of the International Conference on Parallel Processing 1999, 1999

The Index-Permutation Graph Model for Hierarchical Interconnection Networks.
Proceedings of the International Conference on Parallel Processing 1999, 1999

1998
VLSI Layouts of Complete Graphs and Star Graphs.
Inf. Process. Lett., 1998

Pruned Three-Dimensional Toroidal Networks.
Inf. Process. Lett., 1998

Tight Bounds on the Diameter of Gaussian Cubes.
Comput. J., 1998

The Robust-Algorithm Approach to Fault Tolerance on Processor Arrays: Fault Models, Fault Diameter, and Basic Algorithms.
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998

A New Representation of Graphs and Its Applications to Parallel Processing.
Proceedings of the International Conference on Parallel and Distributed Systems, 1998

1997
An on-line fault diagnosis scheme for linear processor arrays.
Microprocessors and Microsystems - Embedded Hardware Design, 1997

A note on architectures for large-capacity CAMs.
Integration, 1997

Cyclic Networks: A Family of Versatile Fixed-Degree Interconnection Architectures.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

Optimal Sorting Algorithms on Incomplete Meshes with Arbitrary Fault Patterns.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

A Class of Fixed-Degree Cayley-Graph Interconnection Networks Derived by Pruning k-ary n-cubes.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

1996
FFT computation with linear processor arrays using a data-driven control scheme.
VLSI Signal Processing, 1996

Comments on "High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits".
IEEE Trans. Computers, 1996

A note on digital filter implementation using hybrid RNS-binary arithmetic.
Signal Processing, 1996

A Generalization of Hypercubic Networks Based on their Chordal Ring Structures.
Parallel Processing Letters, 1996

Extreme-Value Search and General Selection Algorithms for Fully Parallel Associative Memories.
Comput. J., 1996

Parallel Threshold Voting.
Comput. J., 1996

Recursive hierarchical swapped networks: versatile interconnection architectures for highly parallel systems.
Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996

Periodically regular chordal rings: generality, scalability, and VLSI layout.
Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996

Cyclic Petersen Networks: Efficient Fixed-Degree Interconnection Networks for Large-Scale Multicomputer System.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

Numerical Computation on Massively Parallel Processors Based on Residue Number System Arithmetic.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

Performance Analysis and Optimization of Search and Selection Algorithms for Highly Parallel Associative Memories.
Proceedings of the MASCOTS '96, 1996

Comparing the Performance Parameters of Two Network Structures for Scalable Massively Parallel Processors.
Proceedings of the MASCOTS '96, 1996

Design of reliable software via general combination of N-version programming and acceptance testing.
Proceedings of the Seventh International Symposium on Software Reliability Engineering, 1996

Hierarchical Swapped Networks: Efficient Low-Degree Alternatives to Hypercubes and Generalized Hypercubes.
Proceedings of the 1996 International Symposium on Parallel Architectures, 1996

Swapped networks: unifying the architectures and algorithms of a wide class of hierarchical parallel processors.
Proceedings of the 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), 1996

1995
Error Analysis of Approximate Chinese-Reminder-Theorem Decoding.
IEEE Trans. Computers, 1995

SIMD machines: do they have a significant future?
SIGARCH Computer Architecture News, 1995

The Right Acronym at the Right Time.
IEEE Computer, 1995

Robust shearsort on incomplete bypass meshes.
Proceedings of IPPS '95, 1995

1994
Comments on "Evaluation of A + B + K Conditions Without Carry Propagation".
IEEE Trans. Computers, 1994

Fast RNS Division Algorithms for Fixed Divisors with Application to RSA Encrytion.
Inf. Process. Lett., 1994

1993
Alternate memory compression schemes for modular multiplication.
IEEE Trans. Signal Processing, 1993

Optimal Architectures and Algorithms for Mesh-Connected Parallel Computers with Separable Row/Column Buses.
IEEE Trans. Parallel Distrib. Syst., 1993

On the Implementation of Arithmetic Support Functions for Generalized Signed-Digit Number Systems.
IEEE Trans. Computers, 1993

1992
Architectural tradeoffs in the design of VLSI-based associative memories.
Microprocessing and Microprogramming, 1992

Systolic Number Radix Converters.
Comput. J., 1992

Optimal Aspect Ratio and Number of Separable Row/Column Buses for Mesh-Connected Parallel Computers.
Proceedings of the 6th International Parallel Processing Symposium, 1992

Optimal Algorithms for Exact, Inexact, and Approval Voting.
Proceedings of the Digest of Papers: FTCS-22, 1992

1991
High-Performance Parallel Pipelined Voting Networks.
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

New Classes of Unidirectional Error-Detecting Codes.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990
Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations.
IEEE Trans. Computers, 1990

Scalable Architectures for VLSI-Based Associative Memories.
Proceedings of the Parallel Architectures (Postconference PARBASE-90)., 1990

Systolic Associative Memories.
Proceedings of the 1990 International Conference on Parallel Processing, 1990

1989
The Opposite of Common Sense.
IEEE Computer, 1989

1988
Carry-Free Addition of Recorded Binary Signed-Digit Numbers.
IEEE Trans. Computers, 1988

1987
On the Complexity of Table Lookup for Iterative Division.
IEEE Trans. Computers, 1987

Systolic up/down counters with zero and sign detection.
Proceedings of the 8th IEEE Symposium on Computer Arithmetic, 1987

1981
Automatic recognition of printed Farsi texts.
Pattern Recognition, 1981

1979
A Data Structure for Family Relations.
Comput. J., 1979

1978
Detection of Storage Errors in Mass Memories Using Low-Cost Arithmetic Error Codes.
IEEE Trans. Computers, 1978

Optically Weighted Dot-Matrix Farsi and Arabic Numerals.
Proceedings of the Information Technology '78: Proceedings of the 3rd Jerusalem Conference on Information Technology (JCIT3), 1978

1977
Computers and the Farsi Language-A Survey of Problem Areas.
Proceedings of the Information Processing, 1977

1976
Low-cost residue number systems for computer arithmetic.
Proceedings of the American Federation of Information Processing Societies: 1976 National Computer Conference, 1976

1974
A study of fault tolerance techniques for associative processors.
Proceedings of the American Federation of Information Processing Societies: 1974 National Computer Conference, 1974

1973
Design of Fault-Tolerant Associative Processors.
Proceedings of the 1st Annual Symposium on Computer Architecture, 1973

1972
Stochastic Automata and the Problems of Reliability in Sequential Machines.
IEEE Trans. Computers, 1972

A highly parallel computing system for information retrieval.
Proceedings of the American Federation of Information Processing Societies: Proceedings of the AFIPS '72 Fall Joint Computer Conference, December 5-7, 1972, Anaheim, California, USA, 1972


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